搜索资源列表
8-way-responder
- 基于FPGA实现8路抢答器功能 使用芯片为EP2C8Q208C8N,实现40秒内8路抢答功能,八路键盘输入,使用Verilog语言编程,本例子有工程文件、仿真、波形,经过测试可以使用。-8 based on FPGA Responder feature uses chips EP2C8Q208C8N, 40 seconds to achieve 8 Responder features eight keyboard input, using Verilog language programm
FIR_filter
- 基于FPGA实现FIR滤波器功能 使用芯片为EP2C8Q208C8N,实现FIR滤波器的设计,使用Verilog语言编程,本例子有工程文件、仿真、波形,经过测试可以使用。-FIR filter function based on FPGA chip to use EP2C8Q208C8N, achieve FIR filter design using Verilog language programming, the present examples are engineering doc
Digital-clock
- 基于FPGA实现数码管数字时钟功能 使用芯片为EP2C8Q208C8N,使用数码管显示数字时钟,使用Verilog语言编程,本例子有工程文件、仿真、波形,经过测试可以使用。-Based on FPGA digital tube digital clock function uses chip EP2C8Q208C8N, use digital display digital clock, using Verilog language programming, the present exam
Buzzer-music
- 基于FPGA实现蜂鸣器播放音乐的功能 使用芯片为EP2C8Q208C8N,使用普通蜂鸣器,由于频率不同可实现放歌功能,本例设计的是《友谊地久天长》,使用Verilog语言编程,本例子有工程文件、仿真、波形,经过测试可以使用。-Play music based on FPGA buzzer functions using chip EP2C8Q208C8N, using ordinary buzzer, since the frequency of different functions ca
SDRAM
- sdram 状态机驱动源程序工程 完全使用verilog hdl写的-sdram state machine driver source project written entirely in verilog hdl
tlk2711test
- 用verilog语言实现了tlk2711serdes芯片的高速串行功能,包含工程与仿真文件,亲测可用-Using Verilog language to achieve a high-speed serial tlk2711serdes chip function, including the project and the simulation file, pro test available
floatadd
- 32位浮点数加法,使用的语言是verilog。其中包括的是工程中的v文件。-32-bit floating-point addition, the use of language is verilog. Including is v of the engineering documents.
FPGADisplay
- 由ISE开发的FPGA工程文件,显示相关,包括视频接口,用Verilog开发,可以参考学习-ISE developed by the FPGA engineering documents, display related, including video interface, using Verilog development, you can refer to learning
seller_moore
- 用Verilog实现十六进制计数器。内含有整个完整工程。包括tb文件。-realiaztion of timer16 using verilog
timer16
- 十六进制计数器的的Verilog实现。内有整个工程,包括tb文件。仿真可通过-realizaiton of timer16
zongbian4
- 基于verilog语言的差分曼彻斯特编码,内包含数据的采集,CRC校验(8位),和编码,输出。附有完整的工程文件。可直接调用modelsim仿真。-Based on differential Manchester encoding verilog language, and contains data collection, CRC check (8), and coding. With complete project file. Modelsim simulation can be call
verilogiic1121
- verilog ii2c 工程文件-verilog ii2c
RS232-IPcore
- RS232 by verilog,ALTERA 的工程,由几个文件组成,可以参考学习-RS232 by verilog
FPGA_拉格朗日插值_IP
- fpga实现拉格朗日插值,本工程采用verilog语言实现,可直接使用
UART_Send_handle
- 这是一个很好的基于verilog的串口通信422模块,已经经过多次验证,绝对可靠,可直接使用,本人已在工程中多次使用,无误差-This is a good serial communication based on Verilog 422 module, has been repeatedly verified, absolutely reliable, can be used directly, I have repeatedly used in the project, no error
FPGA--study
- FPGA学习的电子课件,PPT最全版,讲述详细,其中第八章还有对应工程的Verilog 代码便于实现调试与设计,并且是都是高级项目,多模块综合形成-FPGA electronic learning courseware, PPT most complete version, about the details, which also corresponds to Chapter VIII of engineering Verilog code debugging easy to implemen
I2C_highway
- 利用硬件描述语言verilog 按I2C总线协议编写了代码,是一个完整的工程,芯片设计中可以参考-Using the Hardware Descr iption Language Verilog according to the I2C bus protocol to write the code, is a complete project, the chip design can refer to
tinycpufiles
- TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程,可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元,外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008),可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is
PipelineCPU
- 一个用Verilog HDL语言所写的32位MIPS指令系统流水线CPU,含代码工程文件和相关设计说明文档,比较详细。-verilog HDL, 32 MIPS pipeline CPU
100Examples
- VHDP入门级教程,实用编程100例,非常适合新手,工程齐全,上手快,是Verilog语言开发工作者的必备代码。-VHDP entry-level tutorial, practical programming 100 cases, very suitable for novice, complete engineering, quick start, Verilog language development workers are essential code.