搜索资源列表
64pointFFTR2MDC
- 该工程实现了一个64点DIF FFT，verilog编写，采用R2MDC结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point DIF FFT, verilog compiled by R2MDC structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the out
IFFT
- 这是关于傅里叶反变换的一个完整的ISE的工程..使用verilog语言-This is on the Fourier transform of a complete anti-ISE project using the verilog language ..
VtoRGB
- Verilog写得BT656视频数据转为RGB数据的Quartus工程文件！-The verilog module for changing BT656 data to RGB data!
PCM30_Frame_Sync
- 本程序实现了PCM30的帧同步和失步检测，采用verilog编程，包含了工程文件。-This procedure achieved PCM30 frame synchronization and detection step, using verilog programming, includes the project file.
DDS__FPGA
- 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容
traffic_lights
- Verilog 语言实现的红黄绿交通灯程序，编译成功，为全工程文件，可以直接打开运行-Verilog language of the red yellow and green traffic lights program, compile successfully, for the whole project file, you can directly open the run
uart2bus_latest.tar
- 文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
LCD
- verilog语言编写的LCD读写代码，包括整个工程-read and write languages LCD verilog code, including the entire project
VGA
- VERILOG编写的VGA实验例程，包括整个工程，可以直接使用-VERILOG VGA written test routines, including the whole project, can be used directly
CoreCFI
- VERILOG编写的CoreCFI实验例程，包括整个工程，可以直接使用-Prepared CoreCFI VERILOG test routines, including the whole project, can be used directly
PCI_LED
- 基于PCI的LED跑马灯程序（verilog工程和上位机工程-PCI-based LED marquee program (verilog project and the host computer engineering
teach~verilog
- 相當完整的VERILOG教程~對初學者或工程師均有不少的助益-Very complete tutorial- for beginners or VERILOG engineers have a lot of help
dct_verilog
- 用FPGA实现dct变换。verilog语言实现，在quartus9.0中验证，含整个工程-dct transform verilog language in quartus9.0 verify, with the entire project
can-bus
- CAN总线控制器的VERILOG工程文件,很实用，工程是ISE可以打开，也可以只使用工程里面的代码-can bus project with VERILOG
Verilog-Niosii-TLC1549
- niosii的一个完整的工程 Q2 软件是9.1版本，里面做了一个TLC1549的AD转换串转并的模块-niosii project with a TLC1549 module
digital-filter
- Verilog语言综合的固定频率的数字滤波器，用于滤除夹杂在固定频率信号上的杂波信号，包含了Quaetus工程和仿真文件。-Verilog language integrated fixed-frequency digital filter for filtering out mixed signals at a fixed frequency noise on the signal contains Quaetus engineering and simulation files.
spacewire_src
- opencores上的关于spacewire的初级源码，已经通过板上实验，但是工程应用有待完善，可以作为设计人员的设计参考-opencores on spacewire on the primary source, the board has passed the test, but the engineering applications need to be improved, can be used as design The design reference staff
UART
- verilog写的串口程序，其功能完全最正确，带工程文件-verilog to write the serial program, its function is completely the right, with the project file
Xilinx-verilog
- xilinx培训源码及工程文件,给予spartan 3E开发板的！希望对初学者有所帮助-Xilinx training codes and project！！ IT‘s worth to learn！！
Verilog
- Zr-tech开发板uart例程基于quartus的工程源代码-Zr-tech development board uart routines based quartus project source code