搜索资源列表
Design_and_Test_VerilogHDL
- Design and Test_Verilog HDL——EDA先锋工作室《设计与验证—Verilog HDL》配书源代码,很多使用的实例,并有说明,是学习Verilog 不可多得的好资料。
sdram_controller
- SDRAM 控制器的 verilog 源代码, 针对Micron 的SDRAMS设计,支持全部的指令, 已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SDRAM controller verilog source code, for Micron' s SDRAMS designed to support all of the instructions, the logic has been verified, and actually used in chip des
verilog_frenqucy_div
- 使用verilog语言实现任意分频的设计,各位verilog学习者或者IC设计验证人员可以参考。-Verilog language use the design of any frequency, you verilog learners or who can refer to IC design verification.
Verilog-Digital-System-Design
- Verilog数字系统设计——RTL综合.测试平台与验证 书中的所有源代码-Verilog Digital System Design- RTL synthesis. Test and verification platform for all the source code for the book
asic_study
- 压缩包中是ASCI学习资料,包括一个台湾中山大学ASIC实验室综合脚本教程,一本springer出版的交大家用system verilog做验证的书,还有一个xilinx论证的XAPP726 - 无线基站基带处理应用中的FPGA的理由。对大家做通信后端设计很有帮助。-ASCI is compressed package learning materials, including a laboratory in Taiwan Sun Yat-ASIC synthesis scr ipts tuto
VerilogDesignand-test_PdfPCode
- Verilog 设计与验证源码+PDF,经典教程,对与RTL和状态机的理解有很大帮助,适合FPGA开发工程师。-Verilog design and verification source+ PDF, classic tutorial, and state machine understanding of RTL helps a lot, suitable for the FPGA development engineers.
Design-and-test-verilog-hdl
- 《设计与验证Verilog HDL》的随书光盘-Design and test Verilog HDL of CD attached with books
DDS
- 基于verilog的DDS设计验证与仿真源代码,在quartus上实现,下载仿真成功-Based on the the the verilog DDS design verification and simulation of the source code, in quartus download simulation success
verilog
- verilog数字系统设计-rtl综合测试平台与验证 书中源码-verilog Digital System Design-rtl test platform verification book source
cshiyan2012
- 基于EDA软件平台上,用硬件描述语言verilog设计完成分频器、计数器、串行移位输出器、伪码发生器、QPSK I/Q调制器、QPSK I/Q解调器,基于选项法中频调制器,再将各个模块综合起来组成一个完整系统;并用quartusII软件对其进行仿真验证。-EDA software platform based on the hardware descr iption language verilog design complete shift of the frequency divider,
Verilog
- RAM ,IFFO实现字节的存储器设计,经过验证-RAM, IFFO bytes of memory design, proven
Verilog-HDL
- 设计与验证:Verilog HDL(清晰带书签)---学习Verilog HDL的很好的资料,这个PDF清晰还带书签,愿能够帮助你。-this material about Learning Verilog HDL is very good
Buzzer-for-verilog
- 在FPGA上设计实现控制蜂鸣器,程序来自实验开发,验证通过。-Designed and implemented in the FPGA to control the buzzer, the program from experimental development and validation through.
bahe
- 采用verilog设计的拔河比赛,在QuartusII9。0仿真验证并在DE2上测试过-Using Verilog to design the tug of war, in QuartusII9. 0 simulation and test on DE2
bingo_spi_test
- 利用SPI实现FPGA和外设之间的通信。经过Modelsim仿真验证。(为FPGA设计技巧与案例开发详解一书源码)(Using SPI to implement communication between FPGA and peripheral. After Modelsim simulation verification. (for FPGA design techniques and case development detailed explanation of a book source
8051-master
- 设计兼容51的指令集的处理器架构 编写兼容51处理器的Verilog代码 仿真 验证测试处理器的功能和性能(The design includes a processor whose instruction set is compatible to the industrial standard 8051 and its FPGA implementation. Through the analysis of instructions, I determine the CPU inte
方波产生
- 设计一个方波产生电路,并进行功能验证和时序验证。(A square wave generation circuit is designed, and function verification and time series verification are carried out.)
PLL
- 本次的设计主要任务是学会调用锁相环 IP 核,并对其进行仿真, 具体要求如下:(1)熟练掌握调用锁相环 IP 核的详细步骤。将 50M 的时钟分成 20MHz 和 100MHz 两个时钟(2)对锁相环进行仿真,验证 调用的锁相环的正确性。(The main task of this design is to learn to call the phase-locked loop IP core.)
jiaotongdeng_fuza
- 本文基于FPGA技术的发展和Quartus II开发平台,实现路口交通灯控制器是一种解决方案。使用Verilog HDL硬件描述语言来描述语言程序的分频器模块,控制模块,数据解析模块,显示译码模块和段选位选模块,五个模块,并通过各个模块程序之间的端口合理连接和协调,成功设计出交通信号灯控制电路。在Quartus II环境下模拟,生成顶层文件下载后,在FPGA EP2C5Q208器件进行验证。(Based on the development of FPGA technology and the
基于FPGA的44矩阵键盘检测设计
- 完成了基于FPGA的矩阵键盘检测设计,使用verilog编程语言,完成了仿真测试验证