搜索资源列表
avr_core2_VHDL
- avr core verilog for asic design
AUDIO_DAC
- 一个关于声音处理的Verilog语言编写的解码芯片,可以用于FPGA处理芯片的IP核,欢迎大家来用。-a voice on the Verilog language decoder chip, FPGA can be used to handle IP core chips, all are welcome to use.
sarm9beta
- arm9 架构简单core实现,可以综合,有实现步骤和说明,verilog代码编写。-arm9 core framework to achieve a simple, comprehensive, implementation steps and notes verilog code prepared.
my_ip_core
- 在quartusII下用verilog语言自己写的IP核,对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
DCTofJPEG
- 用verilog代码写的JPEG压缩核心模块DCT变换之蝶形单元算法-verilog code written using JPEG compression core module DCT's butterfly modules algorithm
vspi
- verilog VSIP core,用verilog语言编写,希望对各位朋友有所帮助!
Ethernet_verilog_ip_core
- Ethernet(以太网)verilog ip core用verilogHDL语言写的以太网软核,对学习verilog语言和以太网有很大帮助。
8255
- Verilog语言描述的Intel8255 IP Core,本人已经在某项目中经过了物理验证的,可直接用于FPGA综合或ASIC综合。
usb1.1_Verilog
- usb1.1的设备控制器IP核,是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
two_d_dct_serial
- altera公司提供的适用于包涵DSP内核的FPGA的二维DCT变换源码,语言是:verilog 性能不错,不过资源消耗有点大,可以用来学习多项式变换的DCT算法-ALTERA companies covered in the application of FPGA DSP core 2D DCT source language is : Verilog performance is good, but a bit large consumption of resources can be us
risc cpu
- risc 8 bit cpu core verilog
VHDL语言实现的arm内核
- 5个ram核,arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核,verilog写的,有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心,结构良好,简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目,国防科技大学牛人ShengYu Shen写的,原来放在opencores上,
mipsdesign
- mips核代码,Verilog写的,希望对大家有用-mips core code, Verilog written
nnARM_core
- nnARM核源代码,用verilog编写,请需要的朋友下来研究,不要用于商业用途-nnARM core source code, using verilog write, please study the needs of a friend down, not for commercial purposes
open_cores_VGAcore
- 老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握-Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the controller and the VGA core gras
8051_source_2.8a
- 8051内核的hdl代码,实际上是verilog格式不过上载页面只有一个vhdl选择,值得一读, 里面对仿真和验证的说明很有含金量-the hdl code of 8051 core
NAND_Flash_Controller
- FPGA实现的NandFlash控制器(带ECC)文档+源代码。-FPGA implementation NandFlash controller (with ECC) document+ source code.
uart2bus
- uart接口到内部总线的IP核,采用VDHL和VERILOG语言编写。-UART interface to Bus IP Core in VHDL and verilog languages
pic10_verilog
- 用verilog实现了PIC10系列单片机的IP核,代码基本来自一篇国外的文章《A Microchip PIC-Compatible RISC CPU IP Core Design and Verilog Implementation》,对一部分进行了改进,主要包括对原文中有一些不可综合的@(posedge clk)语句的改写,使其能通过quartus的编译和综合,并且对跳转部分增加了比较多的注释,这篇文章写得非常好,感谢这篇文章的作者John Gulbrandsen先生,这篇文章让我学到了很多
I2C
- 一个基于Verilog的I2C核的设计,希望对大家有所帮助-Verilog based on the I2C-core design, I hope all of you to help