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i2c.tar
- 是个I2C软核，使用verilog和vhdl实现的，含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
hssdrc_latest
- SDRAM 控制器 Verilog实现，很有借鉴意义。-SDRAM controller core Verilog implementation。With good referential significance.
FPGA_8051core
- FPGA中嵌入8051单片机核的具体操作方法，有图示说明。-8051 single-chip FPGA embedded in the concrete operation of nuclear, there are icons that.
freedev_i2c
- FREEDEV数字应用开发板上的I2C总线IP核的verilog描述-FREEDEV digital application development board I2C bus IP core verilog descr iption of
user_logic_SEG7_LUT_8
- freeDev数字应用开发板中的七段数码管的IP核的verilog实现-freeDev digital application development boards in the seven-segment digital tube of the IP core implementation of the verilog
user_logic_VGA_Controller
- freeDev数字应用开发板中的VGA控制器的IP核的verilog实现-freeDev digital application development board of the VGA controller IP core implementation of the verilog
DDSVerilog
- Verilog 实现的DDS源码，可以配合NiosII软核使用 -Verilog realization of DDS source, you can use with soft-core NiosII
i2cslave_latest.tar
- VHDL/VERILOG FOR I2C Core
usb
- USB完整代码 包括vhdl和verilog两种-usb ip core
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
RS232_NIOS_Verilog
- 5个文件，包含了RS232的nios实现和Verilog实现方式。其中,RS232的nios核实现只需要按照文件描述可以轻松实现^_^，个人比较推荐！RS232的Verilog实现需要编程，例程方便使用。RS232正在进一步学习中，有兴趣的可以探讨。-the realizition of rs232 interface by niosii uart ip core of Altera.it seems a most conveniet way.
wb_lcd
- 基于wishbone的字符型lcd core，支持16×2的字符型lcd显示，verilog语言编写-character lcd core based Wishbone bus, support for 16 × 2' s character lcd display, verilog language
blk_write
- verilog 块ram写入操作 fpga xilinx ip core-Verilog block_ram module fpga xilinx ip core
Chipscope_example
- A easy simple for Xilinx Chipscope Pro, the example shows how to insert cores of VIO, ILA from core generator and verilog code.
i2c
- 该压缩包包含了i2c core设计需要的文献资料以及verilog编写实现i2c通信的源代码-The archive contains the i2c core design requires the preparation of literature and the verilog source code to achieve i2c communication
i2c
- 该压缩包包含了i2c core设计所需的详细时序说明书以及用verilog编写的core的源代码、仿真模块。-The archive contains the i2c core design specifications required for the detailed timing and preparation of the core with the verilog source code, the simulation module.
LIP2131CORE_dram_controller
- LIP2131 CORE Verilog DRAM Controller
cpu
- 本程序主要完成cpu的几个主功能模块的开发，开发语言为verilog硬件语言，基本能模拟cpu的核心功能！-The program mainly to complete the main features of several cpu module development, hardware development language for the verilog language, the basic core functionality can simulate the cpu!
i2c
- I2C IP CORE Verilog quartus-I2C IP CORE Verilog quartusii
source
- FPGA中实现I2C接口的一个IP核，包含verilog及VHDL代码。方便迅速理解和开发I2C总线接口。-FPGA to implement an I2C interface IP core that contains verilog and VHDL code. Facilitate rapid understanding and development of I2C bus interface.