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can_verilog_IP.tar
- 运用Verilog语言编写的CAN控制IP核，符合CAN2.0B协议，仅作为参考！-CAN controller IP core using Verilog language, in line with CAN2.0B agreement, only as a reference!
VGA_CCD531
- 本文围绕一个包含Nios II软核处理器的可编程片上系统展开数码相机的样机设计。论文首先对样机所要达到的整体功能进行了规划，接下来并行开展了软硬件设计。在硬件方面，充分利用了所使用平台提供的SD卡插槽、键盘、数码管、SRAM等各种硬件资源，并用Verilog HDL硬件描述语言设计了样机系统所需要的VGA接口控制器、CMOS图像传感器接口控制器以及VGA显示存储器；在软件方面，本文基于Nios II软核处理器用C语言实现了SD卡的驱动、FAT文件系统的移植、VGA显视器的驱动以及BMP图片文件的
EEthhernet_vet
- Ethernet(以太网)verilog ip core用veriloggHDL语言写的以太网软核，对学习verilog语言与以太网有非常大帮助。 -Ethernet (Ethernet) Verilog the ip core with veriloggHDL language Ethernet soft-core, there is a very big help to learn verilog language and Ethernet.
9b93752447d7
- 用verilog 写的 USB 驱动 适用于SOPC IP CORE-USB drive write verilog. For in the SOPC IP CORE
i2c_master
- I2C master模式的IP core（verilog）-I2C master mode IP core (verilog)
openfire2_latest[1].tar
- VGA 到LVCD verilog 源码，接口为RGB4:2:2 模式可以选择-The OpenCores Enhanced VGA/LCD Controller Core provides VGA capabilities for embedded systems. It supports both CRT and LCD displays with user programmable resolutions and video timings, thus provid
LCD_1602_Interface_IP
- verilog 写的LCD1602 IP核-the LCD1602 IP core verilog write. . . .
viterb_encoder_and_decoder_latest.tar
- Category: Arithmetic core Language: Verilog Development status: Mature Additional info: Design done, Specification done WishBone Compliant: No
minicpu(compiler-8bit)
- CISC microprocessor IP core & 8 bit compiler, verilog语言编写，可在FPGA和CPLD上综合实现,结构类似Intel 8085-CISC microprocessor IP core and 8-bit compiler, verilog language, FPGA and CPLD comprehensive realization .structure is similar to Intel 8085
BuildingPaPRISCPSystemPinPanPFPGA
- 一个32位 RISC CPU 核心，由Verilog 编写而成-A 32-bit RISC CPU core, written by Verilog
divider
- VERILOG编写的24位除法器代码核，是FPGA或者ASIC设计中的一核心计算模块。-VERILOG written 24 divider code nuclear FPGA or ASIC design in a core module.
sqrt
- VERILOG描述的开平方模块核，开方运算是FPGA或ASIC设计中所需要的核心运算模块。-VERILOG descr iption of open square modules nuclear root operation is the core computing module FPGA or ASIC design.
SAR_Send
- 对altera的RS编解码IP核进行仿真，并且写了编解码的控制模块，用verilog实现，通过仿真，编码和解码功能正确。-test of RS code and RS decode,by using quartus ii9.0 with the IP core
ex3
- pll ip核结合七段码 verilog源代码-the pll ip core binding seven-segment code verilog source code
IPCores_iic_8051
- I2C_IP_Core, 使用VHDL 和VERLOG编写，并有文档说明-I2C IP Core, VHDL/Verilog
RD1088_rev01.2
- FPGA或CPLD读取SD卡的IP核，基于wishbone接口，支持SDHC2.0，包含了使用说明，为Verilog语言编写-FPGA or CPLD reads the SD card IP core, based on the wishbone interface, support SDHC2.0, contains instructions for the Verilog language
ethmac10_100M
- 以太网IP Core 它实现10/100 Mbps的MAC控制器功能。它是在IEEE802.3和802.3u 标准下设计实现的。-The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of
fft64
- verilog hdl 编写的64点fft代码，适合很多芯片-coded by verilog hdl that implement 64 point fft, suite to many core
uart16550_latest.tar
- UART16550是较为通用的串口协议，压缩包内有4个文件可供选择，直接提供RTL源码，可直接导入到工程内。-Uart16550 core is used for Serial Commuication.There are 4 folders in the zip package and have the verilog RTL which can be added in the project.
z8051
- 在libero8.1环境下，用Verilog描述的8051内核，可以包括各个基本模块，可以仿真。-In the libero8.1 environment described in Verilog 8051 core, including the basic module can be simulated.