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FFTVHDl
- 基于FPGA的fft实现 摘要：本系统基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核，代替传统DSP芯片或高性能单片机，实现了基于FFT的音频信号分析。-FPGA-based realization of the fft Abstract: This system is based on Altera Cyclone II family of embedded high-performance FPGA embedded IP core
sopcfpga
- 一个Altera Cyclone PCI开发板的配套样板源代码-Sample source code for An Altera Cyclone PCI development board
cyclone_handbook
- Altera 公司生产的FPGA系列中的低端高性能产品cyclone一代用户手册,这个也能从Altera官方网站上下载。-Altera' s FPGA series production of low-end high-performance products cyclone generation, user manuals, this is also downloaded from the Altera website.
VGA_v
- 基于 FPGA 的VGA显示控制器设计（采用Verilog 语言） 控制VGA显示模块 VGA_HS,VGA_VS1,VGA_BLANK时序的发生器。包括测试程序 采用ALTERA Cyclone II系列芯片EP2C8Q208C8N芯片测试成功。-module VGA(CLK_50,RST_N,VGA_HS,VGA_VS1,VGA_BLANK, VGA_CLK,VGA_SYNC,VGA_R,VGA_G,VGA_B) input
meanFilter
- This is a variable length window averaging filter that uses an MCP3002 ADC with SPI interface to sample an analog input, and has a PWM that can be run through a low-pass filter to produce an analog output. The design was simulated in Modelsim with no
test_006
- verilog LCM test , it use Altera cyclone IV GX bord
pci32tlite_oc_latest.tar
- pci32 taget core ip, The core has been designed to permit interface between a PCI Master and simple WHISBONE Slaves, and fitting into smallest FPGA (about 200 LC s in ALTERA CYCLONE II FPGA).-pci32 taget core ip, The core has been designed to p
DE2_user_manual_cn.pdf
- altera de2中文手册:de2提供了实用altera cyclone 2开发高级数字产品需要的所有模块.此为对应用户指南,在30分钟里面,可以浏览许多参考设计.-de2 user manual
CLOCK-ON-ALTERA-DEV-NOARD-RONTEX
- 这是我上电子线路设计课程时自己写的数字钟设计的整个工程.网上下载安装quartus II软件后双击clock.sof打开调试.若软件说没有权限,请删除db文件夹后再试. 文件夹中附带我的实验报告,其中详细讲解了我的设计思路\软件架构\可能出现的问题等等. 调试步骤就不讲了,管脚分配请网友自行完成. 开发板 Altera Cyclone II EP2C35F672C6 软件平台 Quartus II 语言 verilogHDL-These are all the project
Cyclone-FPGA-Family-Data-Sheet
- Cyclone FPGA Family 数据手册。讲述altera公司的FPGA的相关器件。主要用于选型。-Cyclone FPGA Family Data Sheet. Altera about the company' s FPGA-related devices. Mainly used for selection.
altera-cyclone-data-sheet
- Altera结合带有软件工具的可编程逻辑技术、知识产权（IP）和技术服务，在世界范围内为14,000多个客户提供高质量的可编程解决方案。-Altera combines the programmable logic with software tools, intellectual property (IP) and technology services worldwide to more than 14,000 customers with high quality programmable
DDS
- 基于FPGA的DDS直接信号合成器，基于Altera CYcloneII系列-DDS direct FPGA-based signal synthesis, based on Altera CYcloneII Series
da1_test
- ad转换，采用Altera Cyclone FPGA (EP1C6-PQ240)芯片， 在QuartusII 9.0 下编译，有较好的参考价值，已通过测试。-ad conversion, using the Altera Cyclone FPGA (EP1C6-PQ240) chip, in QuartusII 9.0 compiler, a better reference value, has been tested.
Altera-Cyclone1
- ALTERA CPLD\Protel99库_ALTERA\Altera Cyclone II\Altera Cyclone1(PCB/sch.lib)
ALTERA-chip-schematic-and-footprint-
- 比较全的ALTERA芯片的原理图和封装库.rar 使用环境为protel99SE 原来使用一个Cyclone芯片做库时，搜集到的资料。没有问题。-Comparison of the whole of the ALTERA chip schematic and footprint libraries. Rar use environment protel99SE
Cyclone-III-FPGA.sch
- Altera官方Cyclone III实验板原理图，可以作为自己的参考设计-Altera Cyclone III test board official schematic diagram can be used as their reference design
Altera-FPGA-Testing-v1
- This document describes functionality testing of the Altera Cyclone III FPGA Starter Kit Development Board. It also includes testing of associated daughterboards, i.e. the ADA ADC/DAC board and the HSMC to GPIO adapter board.
Altera DE2 TV BOX with Effects Project
- Altera DE2 TV BOX with Effects Project maintaied for Cyclone 2
CCD_Array
- Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.
A4_Clock
- 基于Altera的Cyclone4的时钟程序(clock program based on Cyclone4 of Altera)