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PCIe_Lab(ALTERA-V5PCIe)
- 这一设计实例深入浅出，介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。 -Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.
audio_latest.tar
- Audio Codec(ADPCM 1-Bit) The code is ready for Altera Cyclone-II DE1 Starter board and it is tested, you can modify codes and use them in any project. Core Descr iption: Sampling Frequency: 44100Hz Channels: Stereo Bit-rate: 1 Bit Per Sa
cyclone
- 该文件为Altera 公司低成本FPGA 芯片 Cyclon 的原理图及PCB文件，该电路经过验证，可稳定工作。-This file is a low-cost Altera Corporation schematics and PCB files Cyclon FPGA chip, the circuit proven, stable job.
FIFO_altera.v
- FIFO for Altera Cyclone II or Cyclone III on memory blocks. Length of FIFO can be changed.
VideoSystem
- This project - Altera Cyclone based Videocard - VHDL source.
LCD1602
- 基于altera cyclone 的EP2Q208C8 FPGA的1602液晶显示模块，其中包括驱动模块和测试模块，驱动模块可以作为通用模块，给其他文件调用-Altera cyclone display module is based on the 1602 LCD EP2Q208C8 FPGA, including drive module and test module, drive module can be used as general-purpose modules to other
DDS
- 基于 altera cyclone Ⅳ EP4CE30F23C8N的DDS原理、设计方案以及源代码。可以直接考入开发板使用，内含modelsim波形图，方便仿真使用-Based on the principle of altera cyclone Ⅳ EP4CE30F23C8N DDS, design programs and source code. Can be directly admitted to the development board, containing modelsim w
sync_fifo2
- 基于 altera cyclone Ⅳ EP4CE30F23C8N平台开发。包含了sync结构的fifo2原理、设计方案以及源代码。可以直接考入开发板使用，内含modelsim波形图，方便仿真使用-Altera cyclone Ⅳ EP4CE30F23C8N based platform. Includes sync structure fifo2 principle, design and source code. Can be directly admitted to the develop
altera-soc-cyclone-V
- 针对altera公司的soc平台的开发流程，适用于友晶cyclone v SOC开发板。-Altera soc platform for the company' s development process for Terasic cyclone v SOC development board.
AES-FPGA
- 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA
TestProject
- 用fpga + usb ,fpga 用ep3c10e144 , usb 用釙68013日. 使用nios dma 傳輸數據至cy7c68013 , 經usb 到電腦-it use altera cyclone iii ep3c10e144 and cypress cy7c68013a to pc using nios dma to transmit data to pc via cy7c68013
FFT
- 基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核,实现了基于FFT的音频信号分析-Altera Cyclone II FPGA family based embedded high-performance embedded IP core (Nios) soft core processor to achieve a FFT-based audio signal analysis
DE1_SoC_Audio
- 声音录制、播放的Verilog代码，用于Altera Cyclone V SOC. 写时适配的是DE1-SOC开发板。-Audio recording and playing code for Altera Cyclone V SOC FPGA. Code was designed for DE1-SOC development board, but could be reference for other boards.
2.chaosb_test
- VHDL ALTERA CYCLONE 超声波模块控制代码-VHDL ALTERA CYCLONE
ps2
- 使用verliog实现ps2键盘接口的驱动，通过altera cyclone 第四代验证通过-Use verliog implement ps2 keyboard interface driven by a fourth-generation verified by altera cyclone
vga_interface
- 使用verliog实现vga接口的封装，使用altera cyclone第四代验证通过-Use verliog achieve vga interface package, use altera cyclone verified by the fourth generation
vga_test
- 基于nios的vga控制器,分辨率及显示区域,显示位数,显存深度可调整,已经在altera cyclone ii条件下测试通过 quartus13.0开发环境 主机端符合avalon标准-VGA controller based on NIOS, resolution and display area show the median, the memory depth can be adjusted, has been in Altera cyclone II under the conditi
AD_24bit_Group_25_CYC4
- 高精度24位ADC时钟配置和数据读取程序，基于Altera cyclone IV EP4CE22F17C6N-High-precision 24-bit ADC clock configuration and data reading program, based on Altera cyclone IV EP4CE22F17C6N
DE2-115 Ephoto
- The 4.3" Ultra-high Resolution LCD Touch Panel Development Kit provides users a 800x480 full-color high-quality LCD Touch Panel with complete reference designs and source code allowing users to develop applications by a touch panel on the Altera
dvi_demo
- verilog实现的DVI 视频编码输出与输入，已在altera Cyclone IV 上实现。-DVI encode and decode in Verlog language.Have been tested in altera FPGA Cycloene IV