搜索资源列表
FPGA
- ALTERA FPGA 特殊管脚说明、
BeMicro SDK lab资料
- BeMicro_SDK lab文档,用与学习NIOSii 和Altera FPGA开发
FPGA开发板用户手册
- DE1用户手册,altera公司的FPGA开发板
基于FPGA的软件CDR
- 用FPGA实现CDR,可用于LVDS串化解串,ALTERA原厂工程,实用!
altera signalTap逻辑分析仪
- Altera.FPGA入门及提高教程]SignalTap.II.逻辑分析
FPGA EP2C5Q208/EP2C8Q208原理图和PCB及测试程序
- altera FPGA EP2C5Q208/EP2C8Q208原理图和PCB及测试程序-altera FPGA EP2C5Q208/EP2C8Q208
tftlcd.zip
- TFT LCD controller verilog code using ALTERA FPGA.,TFT LCD controller verilog code using ALTERA FPGA.
jiyu-FPGA-dianziqin
- 1) 主芯片:Altera 的FLEX10K20TC144-4 STC89C58RD+。 2) 要求扩展键盘接口电路,可以实现电子琴的一般功能,进行乐曲的手动演奏,此外还应该具有存储功能,可以将演奏的乐曲进行存储并在人工控制下进行回放。 3) 完成系统方案设计。 4) 编制相应的VHDL程序并进行相应的仿真工作,完成系统的调试工作。 5) 编写51系统程序,完成初始化、系统控制等功能。 6) 利用51系统实现系统的在线配置。 7) 发挥部分 可以进行乐曲的自动演奏。
FIR
- FIR结构数字滤波器,64阶。在Altera FPGA上验证通过-FIR digital filter structure, 64 bands. Verified by the Altera FPGA on the
de0_Schematic
- Altera FPGA DE0的原理图,包含一些经典的FPGA设计电路及相关的接口-Altera FPGA DE0 schematic, contains some classic FPGA design the interface circuit and related
flash_controller
- Altera下的FPGA运行Nios处理器的flash控制器-Altera
word
- Code was successfully implemented within ALtera FPGA with Quartus 6.0. It presents two polish own female names: ULA and ALA whose are scrolling on the 4-columns crystal LED. When you press the switch it will turn from ULA into ALA and continue scroll
EP1C6_EP1C12
- Altera FPGA Cyclone I EP1C6 EP1C12 最小系统 开发板 -the minimum system of Altera FPGA EP1C6 and or EP1C12
niosii
- altera fpga nios2 demo qutarts file
dds
- dds算法的fpga实现 altera 根据不同设置,输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
tut_nios2_introduction
- This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor a
niossramflash
- 在altera FPGA ep3c25器件上实现niosii+sram+flash-Altera FPGA ep3c25 in devices to achieve niosii+ sram+ flash
CIII_NiosII_Small
- altera fpga ep3c25器件niosii处理器最小系统,已编译通过,可直接下载-altera fpga ep3c25 processor minimum system niosii device has been compiled through direct download
EPPTOP
- 在altera fpga中实现epp模式的并口通信程序-epp model of parallel in fpga
a3951ddd-b7c8-4598-b873-4cefbaf1d211
- Altera公司的FPGA器件内带PLL的详细中文使用手册-Altera' s FPGA device PLL with a detailed user manual in Chinese