搜索资源列表
ioasic
- DEC I O ASIC access operations for Linux v2.13.6.
DWC_mctl_ddr_fifo
- ASIC设计中各种同步异步的FIFO实现的verilog source code, 参数可配置 -almost all kinds of FIFO with verilog source code, parametes configuration
ops-sni
- ASIC PCI only supports type 1 config cycles.
qr
- 通过介绍 Q R 二维码 的基本知识及其特点， 然后根据 开放 大学 学生管理 的特点 ，设计 并实现 了开放 大学身份验证 系统， 重 点介绍 了 系统设计 中 的关键技 术。- The b asic know ledge and the features of Q R code are introduced， and then on the basis of the features of the student m an agem ent in op en u nivers ity
ioasic_ints
- Definitions for the interrupt related bits in the I O ASIC.
mr
- The IndigoDJ has no ASIC. Just do nothing.
pcibus_provider_defs
- SN pci asic types. Do not ever renumber these or reuse values.
sh_hspi
- Unusual Devices File for In-System Design, Inc. ISD200 ASIC.
sv_lab_switch
- system verilog ASIC 验证平台编写详细实例-system verilog testbench for ASIC
uvm_lab_switch
- 利用最新的UVM验证方法学搭建完整的ASIC的验证平台。-UVM and svtb for ASIC verification
jbd2
- bfi_reg.h ASIC register defines for all Brocade adapter ASICs.
sizes
- asic design tools rdesc src rdes2c -asm outfile asm bif core defs asm.h. -asic design tools rdesc src rdes2c -asm outfile asm bif core defs asm.h.
StringHexDisplayToNormalDisplay
- labview编写的十六进制转ASIC码的程序框图-block diagram labview written in hexadecimal code switch ASIC
id
- struct dbx500_asic_id - fields of the ASIC ID.
intr_vect
- Interrupt vector numbers autogenerated by n asic design tools rdesc src rdes2intr version.
1
- 舵机位置伺服系统的ASIC控制研究_邱仁贵 介绍了舵机的控制方式和要求 -ASIC Actuator Position Servo System Control _ Qiuren Gui introduced servo control methods and requirements
[elearnica.ir]-4b6b3e354eb48c4917d76defe9c1beea.r
- We consider the problem of tracking mu ltiple maneuvering targets in the presence of clutter u sing switch ing multiple target motion mo d els. A n ovel sub optimal fixed-lag smo othing algorithm is develop ed by applying the b asic interacting mul
egprog
- EG8010 is a digital pure sine wave inverter ASIC (Application Specific Integrated Circuit) with complete function of built-in dead time control. It applies to DC-DC-AC two stage power converter system or DC-AC single stage low power frequency tra
89_full_adder
- 第78例到第89例是一个芯片完整描述的各个部分,但是 它们的源描述所使用的包的源描述超过了演示版限制的300行, 目前不能进行编译与模拟, 如果您需要对其进行编译与模拟,请与北京理工大学 ASIC研究所联系,获取Talent系统的完全版本.-The first 78 cases to 89 cases of the first chip is a complete descr iption of the various parts, but they used to describe the s
89_full_adder
- 第78例到第89例是一个芯片完整描述的各个部分,但是 它们的源描述所使用的包的源描述超过了演示版限制的300行, 目前不能进行编译与模拟, 如果您需要对其进行编译与模拟,请与北京理工大学 ASIC研究所联系,获取Talent系统的完全版本.-The first 78 cases to 89 cases of the first chip is a complete descr iption of the various parts, but they used to describe the s