搜索资源列表
cachesim
- Cache simulator that for any given configuration of direct/associative caches calculates number of hits/misses!
cameralink
- 由于目前基于CameraLink接口的各种相机都不能直接显示，因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统，该系统可以在不通过系统机的情况下，完成对相机CameraLink信号的接收、缓存、读取并显示 系统采用两片SDRAM作为帧缓存，将输入的CameraLink信号转换成帧频为75Hz，分辨率为1 024×768的XGA格式信号，并采用ADV7123JST芯片实现数模转换，将芯片输出的信号送到VGA接口，通过VGA显示器显示
ping_pong_buffer
- 用寄存器来实现乒乓缓存(Verilog HDL)-Ping-pong with the register to achieve cache (Verilog HDL)
ehcache
- ehcache，hibernate的默认缓存，这里做了一个单独使用ehcache缓存的例子-ehcache, hibernate default cache, here to do a separate example of the use of caching ehcache
simulator
- 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is
cache
- （1）FIFO：First In First Out，先进先出 （2）LRU：Least Recently Used，最近最少使用 （3）LFU：Least Frequently Used，最不经常使用-（1）FIFO：First In First Out （2）LRU：Least Recently Used （3）LFU：Least Frequently Used
maze
- 一个迷宫小游戏，透明显示位图，双缓存处理，直截像素处理-A maze game, transparent bitmap display, double the cache handle, deal with straightforward pixels
C64xx_DSP_Cache
- 介绍C64xx DSP Cache的资料，帮助你理解L1，l2的区别-C64xx DSP Cache introductory information to help you understand the L1, l2 distinction
arm_cache
- 这是一个arm处理cache的汇编程序，是一份难得的资料。-This is an arm of the compilation process to deal with cache is a rare information.
ha_cpu-z
- pc config test and check. checking memery, cache, core speed, etc......very fast and pricise
as
- 图像处理中用来显示矩阵测试矩阵操作从缓存给矩阵赋值-Image processing to display the test matrix matrix operations from cache to the assignment matrix
s3c44b0_CACHEtest.tar
- s3c44b0 CACHE测试源码，是嵌入式新手不可不看的经典源码。谢谢站长通过！-err
akala
- java一个国内的开源Java缓存系统-java a domestic system of open-source Java cache
COMBI-Disk
- 一款DOS下的RAM disk和disk cache组合在一起的工具。-A RAM disk under DOS and disk cache combination tool.
cache
- ssd6 联系5 。答案。100分的，共大家参考 -ssd6 Contact 5.答案. 100 points, a total of reference
AT45DB041B-c51pdf
- SPI接口4M位高速存储芯片，带2*512缓存-SPI interface 4M-bit high-speed memory chips, with 2* 512 cache
IECache_src
- 用来清理ie缓存的，rundll32 -u -p 等方式不好用，根据弹出的对话框可以选择清理缓存，比如cookie, ie cache url history等-Ie used to clear the cache, rundll32-u-p not to use such means, according to the pop-up dialog box can choose to clear the cache, such as cookie, ie cache url history, e
Cache_dotnet_cs
- 实现LRU算法的cache dotnet C#源码，用来支持asp.net程序提升系统访问速度。同时保证系统能够控制内存的使用不产生泄漏。-LRU algorithm implementation cache dotnet C# source code, used to support asp.net procedures to enhance the speed of system access. At the same time to ensure that the system be ab
mipscpudesign
- cpu设计实例mips。MIPSI指令集32位CPU （1）MiniCore设计实例全32位操作，32个32位通用寄存器，所有指令和地址全为32位 （2）静态流水线（3～5级） （3）Forwarding技术 （4）片内L1 Cache，指令、数据各4KByte，硬件初始化 （5）没有TLB，但系统控制协处理器（CP0）具有除页面映射外的全部功能 -cpu design example mips. MIPSI instruction set 32-bit CPU (1)
project1_report1
- The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second lev