搜索资源列表
clock_generator
- 802.11a时钟产生、分频模块，verilog源码-802.11a clock generator, frequency module, verilog source
Clock
- 使用远程方法调用，有一个时间发生器和时间显示器，时间显示器可以选择任意的时间间隔来显示时间，并且不同的时间显示器可以分布在不同的机器上，以不同的时间间隔来显示。-The use of remote method invocation, there is a time, generator, and time display, time display may choose an arbitrary time intervals to show time and different time di
ad9523
- AD9523 SPI Low Jitter Clock Generator for Embedded Linux.
CLOCK_GENERATOR
- 一个verilog时钟发生器源代码，能够满足最小时间间隔0.1ns的时钟计时要求。-A clock generator verilog source code, to meet the minimum time interval of 0.1ns clock timing requirements.
si5351
- Si5351A programmable clock generator platform_data.
test_clkgen
- Test Clock Generator. You can learn how to implement test clock generator in VHDL
fram
- Silicon Laboratories Si5351A B C I2C Clock Generator.
clk_gen
- this is a clock generator program by using concurrent language verilog hdl with xilinx ise.
Lab1~3
- 此為VHDL之暫存器、栓鎖器、三態匣、計數與除頻電路以及時脈產生電路-This is a register of VHDL, Latch, tri-state box, count divider circuit and clock generator circuit
mxs
- AD9523 SPI Low Jitter Clock Generator.
qfprom
- Binding for Maxim MAX77802 32k clock generator block.
si5351
- Si5351A B C programmable clock generator platform_data.
maxim-max77686
- Binding for Maxim MAX77686 32k clock generator block.
time60
- 一个占用资源很少的时钟产生Verilog代码，值得借鉴-A small footprint clock generator Verilog code, is worth learning
AD9516_driver_by_STM32
- AD9516是ADI公司的产品，它有14路时钟输出，内部VCO高达2.2GHz，本代码是AD9516的STM32驱动，经验证好使，默认配置为第8路时钟输出270MHz。-AD9516 is a product of ADI which has 14-Output Clock Generator with Integrated 2.2 GHz VCO,this code is the driver of AD9516 ,use STM32.
Pulse-Generator-Final-Zip
- A VHDL pulse generator that generates customizable square wave pulses on an arbitrary number of channels. Controlled by UART communication through serial port. Tuned for 5ns period clock signal. The pulse width and delay of each channel is fully
dwn_sampler
- Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is downsampler FPGA implementation of
1186
- CPU的时钟产生器 根据CLK信号输出4个时钟信号-CPU clock generator 4 under the CLK signal output clock signal
ClockGenerator
- Verilog code for a programmable clock generator
AD652
- Clock generator for AD652-AEC. Generates switchbale 2,174MHz Clock