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key
- cyclone系列下，采用计数器现实案件消抖的verilog HDL语言源码-series under the cyclone, the consumer cases Buffeting counter the reality of the verilog HDL language source code! !
simple_counter
- Simple Counter Written in VERILOG
wishbone_i2c_master
- 本帖最后由 NovaCao 于 1-18-2009 18:02 编辑 使用Quartus II进行仿真 QQ：44425312 QQ群：50585234（群名称：FPGA4u） gtalk：fpgaforu@gmail.com 网站：www.fpga4u.com 淘宝网店：http://shop34914329.taobao.com/ 我们以一个计
iic.cx
- 本帖最后由 NovaCao 于 1-18-2009 18:02 编辑 使用Quartus II进行仿真 QQ：44425312 QQ群：50585234（群名称：FPGA4u） gtalk：fpgaforu@gmail.com 网站：www.fpga4u.com 淘宝网店：http://shop34914329.taobao.com/ 我们以一个计
counters
- 一个用Verilog语言实现的变计数器。包含工程文件和实现文档。-Verilog language implementation with a variable counter. And the achievement of the document contains the project file.
timeclock
- 数字钟的verilog实现程序。包含各个模块。分别为顶层模块，小时计数器，分计数器，秒计数器等。-Digital clock verilog implementation process. With each module. Were top-level module, hours counter, minutes counter, second counter and so on.
AUTO_START
- verilog 编写的代码 方便使用 能自启动的七进制计数器-verilog code written in easy to use can be self-starting of the seven binary counter
bai4
- a 16 bits counter using verilog
counter999
- 采用quartus软件的verilog编程语言编写的计数器模块-Counter module
kbmjsq
- 用Verilog HDL语言实现可变模计数器的功能，并通过Quartus Ⅱ 功能仿真验证-Variable with the Verilog HDL language to counter the function module and function through simulation Quartus Ⅱ
counterN
- A Simple Register Counter in verilog Code with 8 bits
cout_asyn
- 基于verilog的计数器设计，本例程将实现四位异步二进制计数器的功能，同时给出了同步二进制计数器和同步十进制计数器的VerilogHDL程序-Verilog counter based design, this routine will achieve the functions of four asynchronous binary counter, synchronous binary counter is given and synchronous decimal counter Ver
miaobiao
- 秒表实验verilog代码，我已经调试好。希望供大家学习使用。-clock using counter code of verilog HDL.I debug it right
S5
- VERILOG SOURCE CODE FOR N MODULO COUNTER
74hc4017
- 实现的是扭环形十进制计数器，用verilog HDL 语言，在Actel公司提供的LiberoFPGA开发环境下实现，代码经过验证，可在ModelSim中仿真 -Ring is twisted to achieve a decimal counter, using verilog HDL language, Actel offers the LiberoFPGA development environment, the code is validated, the simulation in t
mod6asynchro
- this is a code for mod-6 asynchronous counter in verilog.
asynchro2bitupdownneg
- this a verilog code for asynchronous 2 bit up down counter with negative edge triggered.-this is a verilog code for asynchronous 2 bit up down counter with negative edge triggered.
counter_99
- Verilog实现的倒计数器，从99到1再循环，编译成功，可以直接运行，是很好的verilog语言的例子-Verilog implementation of the down counter, from 99-1 recycling, compiled successfully, you can directly run, is a good example of verilog language
adder1
- 此源代码是基于Verilog语言的“与-或-非”门电路 、用 case语句描述的 4 选 1 数据选择器、同步置数、同步清零的计数器 、用 always 过程语句描述的简单算术逻辑单元、用 begin-end 串行块产生信号波形 ，有广泛的应用，比如编码器领域。-This source code is based on the Verilog language, " and- or- not" gate, with the case statement described in
adder4
- 此源代码是基于Verilog语言的4 位全加器，4 位计数器、 4 位全加器的仿真程序、4 位计数器的仿真程序是用EDA语言描述4 位全加器，有广泛的应用。-The Verilog language source code is based on the 4-bit full adder, 4 bit counter, 4-bit full adder simulation program, 4-bit counter of the simulation program is to use la