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count_seg2
- 采用verilog语言编写，实习双向计数器，并用四段数码管显示。包含四段数码管显示二进制数模块-Use verilog language internship bidirectional counter with four digital tube display. Contains four digital display binary number module
jishuqi
- verilog计数器，很实用，很经典，实际测试过的，免费下载吧，-verilog counter, very practical, very classic, the actual test, Free!
freq_meter
- 使用verilog写的频率计，可切换档位-Frequency counter using verilog write switch stalls
j_k
- jk counter using verilog
count3
- verilog写的一个3计数器。很简单的一个东西。大家闭着眼就能写出来-verilog a 3-counter
three_bits_counter
- verilog 3-bit counter
fPGA_LED
- FPGA开发板做的一个简单LED驱动，使用Verilog语言实现- This is an example of a simple 32 bit up-counter called simple_counter.v It has a single clock input and a 32-bit output port module simple_count(input clock , output end of module counter
fifo-code
- Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
FIFO-and-CAM
- verilog code for gray counter,synchronous and asynchronous fifo
fpga
- FPGA的串口+计数器+DPS+数模转换的VERILOG源代码。-The VERILOG source of digital-to-analog conversion of the FPGA serial the+ counter+DPS+ code.
Freq_counter_ise12migration
- 用verilog实现的一个频率计数器，可分别在不同的频率下计数（自己设定），里面有几个有用的小模块，分频，计数，显示，同步，进位等-Verilog to achieve a frequency counter, respectively, in different frequency count (set), there are several useful modules, divide, count, display, synchronization, binary, etc.
Counter10
- 在quartus 9.1软件上用verilog语言编写的10进制计数器程序-The Verilog language quartus 9.1 software 10 binary counter program
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
count-1
- 基于Verilog的仿真，各个进制的计数器仿真。-Verilog-based simulation, the simulation hex counter.
mb
- 基于Proasic3 startkit 开发板，用verilog语言描述的一个秒表计数器。-Based the ProASIC3 StartKit development board, using Verilog language descr iption of a stopwatch counter.
24xiaoshijishuqi
- 用verilog编写的24小时计数器，可以用作电子时钟，简单易懂。-Written in verilog 24 hour counter, which can be used as electronic clock, easy to understand.
count_0
- 利用控制器和数据通道组成的连续16bits中两个1之间间隔0个数最大的计数器。包括顶层模块，控制器模块和数据通道模块的Verilog源码和时序仿真波形。-Continuous 16bits using the controller and data path in intervals of two between 1 and 0 of the largest number of counter. Including the top module, controller module and da
9999counter
- 用Verilog编写的9999计数器，实现0-9999计数，可任意分频。-9999 counter
PROJECT1-20130414-20130512
- 16bit adder的verilog源代码和4bit的计数器源代码-source code for 16bit adder and 4bit counter
Counter_AD
- Parametrized System Verilog code for a Counter with an increade, decrease switch (AD)