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ji_shu_qi
- 在QuartusII软件中用Verilog HDL编写的计数器的源代码-Verilog HDL prepared counter with in QuartusII software source code
test12
- 自己用VerilogHDL语言编写的时钟程序，包括时钟进位计数模块，数码管显示模块和闹钟模块。在cpld芯片上经测试有效（开发环境没找到VerilogHDL，就选了VHDL，其实他们不一样的……）-Clock with Verilog HDL language written procedures, including clock binary counter module, digital display and alarm modules. The CPLD chip has been te
MATHM60
- 用Verilog语言写程序，实现对初始计数器60进一-Verilog language used to write programs to achieve the initial counter 60 a
Counter_10
- verilog 计数器，每计数到十清零，可以直接下载到DE2-70开发板-verilog counter
8253
- 8253可编程定时器/计数器芯片 VeriLog实现-8253 programmable timer/counter chip VeriLog achieve
calculator
- 利用verilog和vhdl两种语言写作的计数器，还有个性化设计模块，利用quartusii平台写作。-Use verilog and vhdl counter writing in two languages, as well as personalized design module, using the platform quartusii writing.
up_down_counter
- the code is written by verilog HDL, and present a kind of up-down counter to realize triangle carrier
part1
- a 4-bit synchronous counter using T-Flip Flops and AND gates in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
counter10
- verilog编写的10进制计数器，并且功能仿真正确。软件为quartus II 11.0,和Modelsim-verilog prepared 10 binary counter, and functional simulation is correct. Software quartus II 11.0, and Modelsim
siweijishu
- verilog 四位十进制计数器 已经仿真正确-verilog four decimal counter
daima
- 这是一个频率计的verilog源码 实现频率计数-this is a verilog program,it content a example impliment a frequnt counter.
sync_reset_counter
- verilog语言四位计数器 使用clock always block-verilog language four counter clock always block
Counter_Debounce
- Verilog 3-bit Inc/Dec Counter on Spartan3E
count
- basys2 模60计数器 并用数码管显示 verilog FPGA-basys2 mold 60 counter digital display
counter7
- 4bit counter in verilog
kaoshi
- FPGA -计数器，29减法计数器。使用verilog hdl编写格式，cyclone I 系列EP1C3TC144芯片。-FPGA programming using 29 down counter, using verilog hdl written format, cyclone I series EP1C3TC144 chips.
fp24_prj
- 这是我利用Verilog编写的一个时钟计数器，包括了时钟分钟和秒，结构简单，功能细化，而且我也将仿真结果放在该压缩文件中，通过下载到FPGA的板子当中就可以实现计数，希望对初学FPGA的同学有帮助-This is what I use Verilog prepared a clock counter, including the clock minutes and seconds, simple structure, function refinement, and I will also be
johnson
- verilog语言,johnson计数器的设计-johnson counter
test_led
- Verilog语言的24小时计数器，数码管显示，按键调时，在CPLD上调试正常。-Verilog language 24-hour counter, digital display, when the key tone on CPLD normal debugging.
Lab13_mod5cnt
- 模-5计数器就是从0到4重复计数。也就是说，它一共要经历5个状态，输出从000变到100然后再回到000。本实验中用Verilog语句来描述。-Module-5 counter is from 0 to 4 repeat count. That is to say, it has to experience 5 state, the output from 000 to 100 and then to 000. Using the Verilog statement in this experi