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S2_counter
- 用verilog HDL语言编制的计数器，并且可以在开发板上以灯亮灭体现功能，Xilinx的Spartan6系列芯片。-Counter with verilog HDL language preparation, and the development board to be light reflected off function, Xilinx' s Spartan6 series chips.
code
- 基于Verilog HDL 1、div为分频模块,晶振50M,目的是得到1HZ 2、cnt为异步清零，同步加载，同步使能的十二进制计数器。-4-Bit Binary Up Counter with Asynchronous Clear, Synchronous Load, and Asynchronous En.
counter8
- 8 位 计数器，带使能键和重置键。附带testbench, verilog 环境-8 bit counter
DFF_div2
- 基于DFF的2分频器，verilog环境， 门级描述-based on DFF counter 2, gate level
counter_exercise
- Verilog语言实现计数器的功能和仿真-Verilog language and simulation functionality counter
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
module-counter8
- 用verilog实现8为计数器频率范围20-80kHz，根据DDS原理来一个时钟计数器记一下，n=n+1，根据公式fout=（fc÷x）÷2，fout=80 fc=320，所以n≥2时，再取反，又由公式 fout=(k.fc)÷2^n，k=50hz，fout=80khz，fc=320，所以数据的位宽n≥7。 设计要求两路方波信号的相位差在0-360゜可调，可以根据延时来实现。具体的-8 is realized with verilog counter frequency range 20-8
cnt201403010
- verilog写的计数器，很简单的一个计数功能，供初学者参考学习-verilog write counter, very simple counting function reference for beginners to learn
count15
- 用verilog语言实现15进制加法计数器的功能-Achieve 15 binary adder counter function using verilog language
counter_johnson
- 基于FPGA,CPLD嵌入式系统的Verilog语言，用于实现Johnson计数器。-base on the FPGA or DPLD，to complement the Johnson counter.
codes
- 5 simple verilog codes: Arithmetic.v - arithmetic operations on verilog Accumulator.v - 8 bit adder accumulator counterfpga.v - 4 bit up counter w/ fpga code UpDown3.v - 4 bit Up-down counter w/fpga code pattefier.v - pattern/sequence ident
Counter8bit
- This is an 8 bit Up Counter coded using Verilog HDL. Bus width can be edited to your desired specs.
UpDownCounter
- This is an Up Down Counter coded in Verilog HDL. You can edit the bus width of this.
UpDownCounter_FSM
- This code is an Up Down Counter in FSM using Verilog HDL.
displayCounter2.tar
- Verilog example of a program that uses a 7 segment display (included in fpga) to display a counter 0 to 99. Implemmented in FPGA Nexys3-Verilog example of a program that uses a 7 segment display (included in fpga) to display a counter 0 to 99. Imple
start_lab4
- 用Verilog设计一个时间基准电路和带使能的多周期计数器，并在此基础是设计一个简单的秒表0.0-10.0计数- Verilog design with a time reference circuit and with enable multi-cycle counter, and on this basis is to design a simple stopwatch count 0.0-10.0
counter2
- 附件包括两个内容1.采用Verilog编写的的十进制计数器的ISE工程2.代码文档一份。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Appendix includes two contents of 1 written by Verilog decimal counter of the ISE project a 2 code document. The software platform is ISE13.3, the hardware platform is Spart
S2_counter_NEW
- 设计一个以十进制为基础的计数器，实现从 0 开始的计数功能；本实验主要是利用开发板上面的数码管实现一个十进制计数器的功能，计数范围0000-9999，可实现循环计数。先输入verilog 程序，然后在 QuartusII 中做波形仿真，通过后下载程序在数码管上查看计数器的功能。-Designing a decimal-based counters, a zero-counting function this experiment is the use of digital control b
Desktop
- verilog 实现的可逆计数器及4-7译码器，实现并行置数，加减计数功能 -verilog achieve reversible counter and 4-7 decoder, set the number of parallelism, subtraction counting function
freq_cnt
- Frequency Counter in Verilog