搜索资源列表
TLC1620
- 基于FPGA的Verilog语言实现的六十进制计数器-FPGA-based Verilog language implementation of six decimal counter
fp_verilog
- 用Verilog编写的分频计数器，实现分频。-Written using Verilog-scale counter.
counter_4bit
- 4 BIT COUNTER USING VERILOG
frequency-meter---DEII
- verilog写的频率计 ，在数码管上显示10进制输入数字信号的频率。已在DEII上验证- verilog write frequency counter, decimal display frequency of the input digital signal in the digital tube. Verified on DEII
trtgh4P944
- 8位十进制计数器,采用Verilog语言编写，成功与大家分享一下-8-bit decimal counter, use Verilog language, to share with you about my success
08_counter_white
- verilog HDL 计数器 8位 计数值送数码管显示-this is a verilog file for counter
FPGA__source-code__Verilog
- FPGA部分基础功能源代码，适合初学者进行学习仿真，代码可读性强，通俗易懂，逻辑清晰。包括触发器，全加器，分频，并串转换，计数器，序列发生器等Verilog语言源代码。- Part of the basic functions of the source code for FPGA.Suitable for beginners to learn the simulation, the code readable, easy to understand, clear logic. Includ
Timer_design_XUP
- verilog写的秒计数器，计数结果显示在四个七段四个数码管上，两个作为秒位，两个作为分钟位。-A seconds counter described by verilog, counting results are displayed on the four seven four digital tube, two as second bit, two as a minute bit.
counter6display
- ISE环境下Verilog变成实现六位计数器并用7段显像管显示-ISE Verilog environment becomes realized under six counter with 7-segment display CRT
cnt63dis
- ISE环境下Verilog编程实现63进制计数器并用7段译码显像管显示-ISE Verilog programming environment under 63 binary counter with 7 segment decoder CRT display
Verilog_counters
- 12-modulo counter in Verilog. Counts up and down, devides by 2, stops, resets. If <5 Y = 1 . Counter.v is behavioral, counter_b.v - gates level.-12-modulo counter in Verilog. Counts up and down, devides by 2, stops, resets. If <5 Y = 1 . Count
Frequency-divider
- 利用Verilog设计的在停车场情况下的模拟的分频器和计数器的代码-The use of Verilog design in the parking lot in case of analog frequency divider and counter code
Timing-
- 利用verilog设计的停车场中的计数器计时器和计费器，完成智能管理效果-Use the counter timer and meter parking lot in the Verilog design, intelligent management
Comparator
- Verilog program for an 8bit up down counter
homeworkreal
- 自己做的一个简单地verilog 程序，仿真了计数器-This is a simple program in verilog.It compelte functions including counter.
counterbcd
- 这是计数器的波形仿真文件属于vreilog的时序仿真-this is a verilog waveform file of a counter
count
- 用Vrilog实现了一个计数器，并用七段数码管进行显示，运用了时分复用，代码简单明了，适合基础学习。-Using Verilog to achieve a counter, the code is simple and clear, suitable for basic learning.
up_counter_8
- Code for 8bit up counter in Verilog
jishuqi
- 这是Verilog写的，一个计数器的程序代码，以及测试文档-This is written by Verilog, a program code for the counter, and a test document
EDA
- 熟悉QuartusⅡ的Verilog HDL文本设计流程全过程，学习计数器的设计、仿真和硬件测试。-Familiar with Quartus II Verilog HDL text design process, learning counter design, simulation and hardware testing.