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counter
- 基于CPLD的计数器 实现光纤测距，包含与单片机的时序控制 Verilog 实现 通过仿真
基于verilog的38译码器
- 基于verilog的38译码器，八个输出，三个输入-counter based on verilog
ledcount60.verilog语言书写 用数码管显示
- verilog语言书写 用数码管显示，60位的计数器，加上分频模块可以实现时钟功能,verilog language digital display, 60-bit counter, together with the sub-frequency clock function modules can be achieved
counter.rar
- 初学者学习modelsim的好例子，基于Verilog的计数器，带测试源码，在quartus2运行。,Modelsim beginners to learn a good example of Verilog based on the counter, with the test source code, running in quartus2.
pld MegaWizard Plug-In Manager
- 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_
tlc5628VHDL
- VHDL实现对TLC5628 AD芯片的时序控制,vhdl对时序的控制不仅高速,而且控制时序清晰,容易实现-vhdl counter tlc5628
counter_3
- 三种计数器的verilog实现,二进制计数器,格雷码计数器,约翰逊计数器.初学硬件描述语言可参考。-Three kinds of counter verilog implementation of a binary counter, gray code counter, Johnson counter beginner hardware descr iption language can refer to
8253
- 8253计数器接口电路 intel8253是NMOS工艺制成的可编程计数器/定时器，有几种芯片型号，外形引脚及功能都是兼容的，只是工作的最高计数速率有所差异-8253 counter interface circuit
a_time_counter_using_verilog
- a time counter using verilog
count
- 一种计数器的FPGA的verilog源程序和仿真图谱-A kind of counter verilog source code and simulation of FPGA-map
verilog
- 包含了许多verilog编程的实用例子，且有运行之后的V文件，很完整-verilog
HW3
- Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts d
pinlvji
- 自己编的一个频率计，verilog语言写的，用数码管显示方波的频率，测量量程是0.1hz~9999999hz，测方波的稳定性极高。-Their series a frequency counter, verilog language written with the digital display of the square wave frequency, measurement range is 0.1hz ~ 9999999hz, high stability of the square w
Variable-mode--counter
- 这是可变模加减计数器的Verilog源程序，已经编译通过，可以使用-This is the variable mode subtraction counter Verilog source code, has been compiled by, you can use
Four-adder-and-four--counter
- 4位全加器和计数器的verilog的例程，还有四位全加器的仿真程序。-Four QuanJia device and counter verilog of the routines, and four QuanJia device simulation program.
counter
- 计数器实现的verilog代码，基础的实用，大家多多支持-Counter verilog code to achieve, based on practical, we can support
Counter
- Verilog documentation
verilog.tar
- please check the english descr iption.(an counter example written by verilog.)
Johnaon_counter
- 本设计为六位约翰逊(Johnson)计数器，首先给大家介绍一下什么是约翰逊计数器，它又称扭环计数器,是一种用n位触发器来表示2n个状态的计数器。它与环形计数器不同,后者用n位触发器仅可表示n个状态。2~n进制计数器(n为触发器的个数)有2~n个状态。若以6位二进制计数器为例,它可表示64个状态。但由于8421码每组代码之间可能有二位或二位以上的二进制代码发生改变,这在计数器中特别是异步计数器中就有可能产生错误的译码信号,从而造成永久性的错误。而约翰逊计数器的状态表中,相邻两组代码只可能有一位二进
verilog
- 8位计数器，可以实现计数器的相关功能，内涵verilog文件和testbench文件(8 bits counter,include v and testbech files ,has the ability of 8 bits counter)