搜索资源列表
counter
- 用verilog实现基于FPGA的计数器功能实现-Realization of counter function based on FPGA with Verilog
gray_counter
- altera官方格雷码计数器的verilog代码和testbench,已测试-altera official Gray code counter verilog code and testbench, have been tested
second-and--minite-and-hour-counter
- 利用Verilog语言实现时分秒计时功能，并用modelsim仿真出波形。-implementate when minutes timing function using Verilog language, and simulating waveform in the modelsim
BCD-Counter
- Verilog Module for parity
counter
- Counter using Verilog
n_Bit_Counter
- n bit counter verilog code
verilog_PLL
- 全数字锁相环的verilog源代码，包括鉴相器，K变摸可逆计数器，加减脉冲器和N分频器。已经仿真实现。(All digital phase-locked loop Verilog source code, including phase discriminator, K variable touch reversible counter, add and subtract pulse and N frequency divider. Have been implemented by simula
Johnson
- 这个是一个计数器的程序，能够帮助初学者有效的理解计数器(This is a counter program, can help beginners effectively understand the counter)
FreqCounter_1_12
- verilog code on frequency counter
timing
- Verilog实现计数器并送六位数码管实时显示(Verilog realize the counter and send six digital tube real-time display)
async_counter_verilog
- 这是用verilog 实现的同步计数器。(this is a code for synchronous counter written in verilog.)
cnt12
- 十二进制计数器，基于verilog HDL实现。(Twelve decimal counter)
计数器
- 简单的硬件描述语言verilog语言描述的128进制计数器。(Simple hardware descr iption Language Verilog language described 128 binary counter.)
deng
- 模60计数器，适应verilog 语言实现，一个小程序，联系制作(A module 60 counter, implemented in the Verilog language)
gray_counter
- 格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换(Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conve
spi
- 通过SPI接口给一段位宽16位长度为8的配置寄存器进行赋值。位宽为16 表示存储的数据信息位数为16，长度为8，则代表的是寄存器的深度为8。 在输入第一位数据时，定义一个计数器count，以判断目前接收了几个数据。当接收到第8位时，后六位为地址，前两位用于判断，10表示读操作，11表示写操作，进入读写操作后仍需计数，以便判断何时读完或写完，当count=24时为读写操作完毕。(Through the SPI interface to a 16 bit length 8 configuratio
timer0
- 一个简单的timer，包括定时器，计数器功能模式，非常实用，供参考(A simple timer, including timer, counter function mode, very practical, for reference.)
src
- 基于AXI 总线的可配置脉冲计数器，可以配置计算脉冲的个数。(The configurable pulse counter based on AXI bus can be configured to calculate the number of pulses)
黑金Altera开发板Verilog实例教程
- 控制开发板上的4个LED灯，计数器记到4秒清零，控制LED灯依次亮(Controlling the four leds on the development board, the counter down to the 4 seconds reset, the control the LED light in turn)
New folder
- verilog codes for counter,d flipflop,fibonacci series,prime numbers,top.