搜索资源列表
beipin_quartII
- 在FPGA或CPLD上实现的一中非常实用的倍频电路，只要输入频率高，精度就很高-the CPLD or FPGA to achieve a very practical frequency circuit, as long as the input frequency, on the high precision
cpld_line_cnc
- 关于用CPLD和FPGA做插补算法的内容,对于想用FPGA做控制的朋友是个好的借鉴!-on with CPLD and FPGA done interpolation algorithm, for to do with the control of the FPGA is a good friend from!
Altare_beginner
- Altare公司训练新人的练习题下载.rar FPGA/CPLD-Altare company's new training exercises download. Rar FPGA / CPLD
fpga_cpld
- 一份fpga/cpld的入门教程，对初学者很有帮助。-a fpga / cpld introductory tutorial for beginners helpful.
VerilogHDL88
- veriloghdl语言工具书，适合初次了解cpld和fpga工程师学习使用-veriloghdl language tool, suitable for initial understanding of fpga and cpld engineers learning
vhdlcodes
- FPGA/CPLD集成开发环境ISE的使用详解 示例代码1-FPGA / CPLD Integrated Development Environment ISE Comments on the use of a code sample
vhdlcodes2
- FPGA/CPLD集成开发环境ISE使用详解实例－2-FPGA / CPLD integrated development environment IDE ISE examples -2
vhdlcodes3
- FPGA/CPLD集成开发环境ISE使用详解实例－3-FPGA / CPLD integrated development environment IDE ISE example -3
vhdlcodes4
- FPGA/CPLD集成开发环境ISE使用详解实例－4-FPGA / CPLD integrated development environment IDE ISE example -4
vhdlcodes5
- FPGA/CPLD集成开发环境ISE使用详解实例－5-FPGA / CPLD integrated development environment IDE ISE example -5
vhdlcdes6
- FPGA/CPLD集成开发环境ISE使用详解实例－6-FPGA / CPLD integrated development environment IDE ISE example -6
FPGA_CPLDdigitalcircuitexperience
- FPGA和CPLD设计时的经验和大家一共分享，开发FPGA时很好的资料-FPGA and CPLD design experience and we were sharing, FPGA development when good information
vhdlcodes7
- FPGA/CPLD集成开发环境ise的使用详解 示例代码7-FPGA / CPLD integrated development environment IDE ise the sample code 7
vhdlcodes8
- FPGA/CPLD集成开发环境ise的使用详解 示例代码8-FPGA / CPLD integrated development environment IDE ise the sample code 8
vhdlcodes9
- FPGA/CPLD集成开发环境ise的使用详解 示例代码9-FPGA / CPLD Integrated Development Environment ise Comments on the use of code examples 9
vhdlcodes10
- FPGA/CPLD集成开发环境ise的使用详解 示例代码10-FPGA / CPLD integrated development environment IDE ise the example code 10
vhdlcodes11
- FPGA/CPLD集成开发环境ise的使用详解 示例代码-FPGA / CPLD integrated development environment IDE ise the example code
cpldfpga
- 详细描述了在FPGA/CPLD设计过程中应注意的地方,和如何提高设计效率,对FPGA设计者有很好的帮助-detailed descr iption of the FPGA / CPLD design process should be noted, and how to improve design efficiency and FPGA designers to have a good help
digital_clock
- 用verlog语言编的一个很好的综合实验,特别适合于FPGA/CPLD的初学者-verlog language with a good addendum to the comprehensive experiment, particularly suitable for FPGA / CPLD beginners
traffic_lamp
- 用verlog语言编的又一个很好的综合实验(交通灯的控制),特别适合于FPGA/CPLD的初学者-verlog language used is an addendum to the good of the experiment (traffic light control), particularly suitable for FPGA / CPLD beginners