搜索资源列表
Xilinx_TFT_serial
- 基于FPGA/CPLD平台的640*480分辨率的TFT-LCD控制器,通过UART口接收外部输入信号-Based platform FPGA/CPLD 640* 480 resolution TFT-LCD controller, an external input signal received through the UART port
IIC_MasterDriver
- IIC主机控制vhdl源码,支持IIC普通和快速模式,多个fpga/cpld平台已验证-IIC host control source code,normal and fast mode support
AlteraPFPGA_CPLD
- FPGA和CPLD的学习资料,从初级到高级,从基础到深入,对于学习FPGA的初学者很有用处。-FPGA and CPLD learning materials, from beginner to advanced, from basic to in-depth for beginners learning FPGA useful.
FPGACPLD-design-tools-Xilinx-ISE
- FPGA/CPLD设计工具──Xilinx ISE使用详解!x详细介绍了XilinxISE的使用方法!-FPGA/CPLD design tools ─ ─ Xilinx ISE explain the use of! x details use XilinxISE!
ise1
- ise教程,Xilinx FPGA/CPLD设计手册 Xilinx公司推荐FPGA/CPLD培训手册-ise for Xilinx FPGA/CPLD
nano-logic
- 本手册适用于使用NANO-LOGIC CPLD 系列开发板的用户。 一款较高端FPGA 开发板既可以做项目开发也可以配上一个“通用的基础设备接口 板”作为新人培训入门使用 本产品的推出旨在于方便用户扩展基础设备和初学者学习使用。在FPGA 产品的设计 中,在初期调试时为了方便调试和显示程序工作状态,经常会用到大量的调试接口,比 如灯、按键、液晶显示等设备;这些设备既浪费有限的FPGA 资源又浪费宝贵的板卡体 积。本开发板提供了通常用户调试程序所需要的基础输入输出和上位机通
VHDL-divider-design
- VHDL分频器设计,本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计,包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数(N+0.5)分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-cr
keyboard
- fpga/cpld按键扫描vhdl语言代码(4x4按键阵列)-Fpga/cpld keypad scanning VHDL language code (4x4 scan)
FPGA_CPLD-SHC
- FPGA_CPLD-SHC多款FPGA CPLD开发板的原理图,很好的线路设计参考-FPGA_CPLD-SHC Variety of FPGA CPLD development board schematics, a good reference circuit design
PARITY-CHECK
- this vhdl code for parity check is very helpful while coding and decoding , Implementing this in an cpld of fpga is very easy and it can be used as a subpart of any embededd design such as multiplexers , Decoders etcv -this vhdl code for parity check
omu_b
- CPLD的功能实现,主要有FPGA配置、寄存器定义、两种分频等内容-The realization of the function of the Slave SerialCPLD, basically have FPGA configuration, register definition, two kind of frequency division, etc
RD1088_rev01.2
- FPGA或CPLD读取SD卡的IP核,基于wishbone接口,支持SDHC2.0,包含了使用说明,为Verilog语言编写-FPGA or CPLD reads the SD card IP core, based on the wishbone interface, support SDHC2.0, contains instructions for the Verilog language
GalDevicesApplicationDesign
- 手把手教你学GAL器件应用设计 在深圳,一位 CPLD(可编程逻辑器件)设计人员的工资是月薪 1万元,而且还万金 难求。现在 FPGA/CPLD/ARM等芯片设计技术已越来越多地应用在产品开发中,本文 就是您通往芯片设计殿堂的起点。 -The GAL devices application design taught you to learn
ch2
- VHDL技术教程 第二章;第二章分为概述、简单PLD结构原理、CPLD结构原理、FPGA结构原理等其他概述介绍-TECHNOLOGY OF VHDL U2
VHDL-for-beginners
- VHDL for beginners. This file contain a few pdf s about distinguishing characteristic. Needed knowledge about VHDL in FPGA/CPLD.-VHDL for beginners. This file contain a few pdf s about distinguishing characteristic. Needed knowledge about VHDL in FP
abc
- 在Quartus II 9.1下开发FPGA/CPLD程序的使用教程操作笔记-Quartus II 9.1 developed under the operation of the FPGA/CPLD program using the tutorial notes
Altera-FPGA_CPLD-design
- 《Altera FPGA-CPLD设计》一书的实例源代码。非常适合FPGA初学者。-" Altera FPGA-CPLD design" book source code examples. Very suitable for FPGA beginners.
vhdl-serial
- VHDL串口通信,实现数据的发送与接收,适合FPGA和CPLD芯片的开发-VHDL serial communication
test3
- 中断闪灯(CPLD)文件夹中为FPGA部分程序,中断闪灯(DSP)文件夹中为DSP部分程序。中断闪灯(CPLD)中主要是提供DSP工作中所需要的相关信号。在中断闪灯(DSP)中主要实现外部的开关按钮S1的触发产生中断,DSP接收到相关中断信号后,跳转到闪灯子程序中,指示灯HL4开始闪烁。-Interrupt flash (CPLD) folder for FPGA part of the program to interrupt flash (DSP) folder for the DSP pa
CummingsSNUG2002SJ_FIFO1_rev1_1
- FIFO设计,采用verilog语言编写,相当不错,验证可行-Altera FPGA CPLD design (Basics) CD-ROM1