搜索资源列表
seg7_8
- fpga cpld verilog hdl 语言 代码程序 数码管 控制
lcdname2(santez)
- this program is used to dislay a text on lcd .the language is verilog and it can be usedto program FPGA OR CPLD
digitalclock
- digital alarm clock on lcd- written in verilog to program fpga or cpld
temp
- 用fpga/cpld驱动温度传感器lm75，用数码管显示温度-With fpga/cpld drive temperature sensor lm75, with digital display temperature
Altera-FPGA_CPLDdesign
- altera的cpld和fpga基础知识学习，对初学者很有帮助。-altera cpld and fpga basics of learning, useful for beginners.
Altera-FPGA_CPLD-Design
- Altera FPGA/CPLD设计（基础篇），非常好的 FPGA入门教程-Altera FPGA/CPLD design (Basics), very good FPGA Tutorial
201093144828520
- 结合足球机器人视觉系统介绍嵌入式图像采集和处理系统的一些新方法，设计了基于FPGA/CPLD的嵌入式图像采集与处理系统。-Some new method combines soccer robot vision system introduces embedded image acquisition and processing system is designed based on FPGA/CPLD embedded image acquisition and processing syst
add128
- 128位的地址译码器，在cpld或者fpga上实现兼可-128-bit address decoder, in the CPLD or FPGA implementation and may
c_motor
- vhdl实现的直流电机控制器 通用程序 对不同fpga/cpld，可能需要修改部分源代码。-vhdl to DC motor controller General Procedure Different fpga/cpld, may need to modify some of the source code.
AD7982
- 基于FPGA/CPLD的数据采集处理系统，应用芯片AD7982实现十八位高速数据采集，串行输出。基于VHDL语言的完整AD7982 的程序。-Based on FPGA/CPLD data acquisition and processing system, the application achieved eighteen chip AD7982 high-speed data acquisition, serial output. AD7982 is a complete VHDL lang
Embedded-Hardware-Training.pdf
- 本书内容非常丰富，共分为3部分。第一部分：常用电路及元件。第二部分：PROTEL DXP.第三部分：FPGA/CPLD技术。-This book is very rich, is divided into three parts. Part I: Common circuits and components. The second part:. PROTEL DXP third part: FPGA/CPLD technology.
SVPWM_FPGA_ContainSourceCode
- 广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。-Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is propose
arm
- 此程序是ARM+FPGA的总线通信程序，我只提供FPGA这一边的，其实我现在把这个程序移植到dsp+cpld上面去了，那个程序其实都出不多-This program is ARM+ FPGA bus communication procedures, I only FPGA side, in fact, I now put this program ported to dsp+ cpld go above, and that the program actually much
fpga-cpld
- 数码管的显示，跑马灯-Digital tube display, marquees。。。。。。。。。。
testbeach
- 适用于cpld或fpga，产生多种频率波形，-Apply to cpld or fpga, generate multiple frequency waveform,
vhdlcodes10
- FPGA/CPLD集成开发环境ise的使用详解 示例代码10-FPGA/CPLD integrated development environment IDE ise the example code 10
vhdlcodes11
- FPGA/CPLD集成开发环境ise的使用详解 示例代码-FPGA/CPLD integrated development environment IDE ise the example code
vhdlcodes9
- FPGA/CPLD集成开发环境ise的使用详解 示例代码9-FPGA/CPLD Integrated Development Environment ise Comments on the use of code examples 9
LED_Counter
- this code show how to use Altium to coding LED Counter on FPGA-CPLD
LEDglow
- this code show how to use Altium to coding LED glow on FPGA-CPLD