搜索资源列表
manchester-Xinlinx
- verilog代码： 基于cpld的machester编译码器-verilog code: cpld of machester based codec
ex1_clkdiv
- Verilog语言编写，通过此代码控制CPLD输出任意偶数倍分频-Verilog language, through this code control CPLD any even multiple output divider
ps2scan
- 采用VERILOG的CPLD编程，通过ps2接收键盘数据，然后把接收到的字母A到Z键值转换相应的ASII码，通过串口发送到PC机上。 -Using VERILOG CPLD programming, through the PS2 receive keyboard data, and then receive the letters A to Z key transformation corresponding ASII code, through the serial port to se
shift-register
- FPGA/CPLD 的verilog移位寄存器代码。-verilog shift register code.
ILX554B_CPLD
- 用CPLD（EMP240T100C5）产生ILX554B的驱动时序，CCD的驱动时序电路程序。用verilog编写。-Drive timing generator ILX554B with CPLD (EMP240T100C5), CCD drive timing circuit program. Written in verilog.
LCD1602
- Verilog 语言 CPLD 控制液晶自定义输出程序，可仿真，可转换电路原理图。-Verilog language CPLD control LCD custom output procedures, can be simulated, can be converted to circuit schematics.
Verilog_prj
- 特权同学BJ-EPM240 CPLD开发板配套视频源码文件，ex1~ex15全，是入门Verilog的首选。-Privileged students BJ-EPM240 CPLD development board supporting the video source files, ex1 ~ ex15 whole, is the first choice of entry Verilog.
receive_spi
- verilog语言SPI通信，可用于CPLD以及FPGA-Verilog language SPI communications, can be used for CPLD and FPGA
RS485
- FPGA/CPLD实现RS485通信协议，在Quartus ii平台上进行Verilog编程仿真-FPGA/CPLD realize RS485 communication protocol used to Verilog simulation on Quartus ii programming platform
ex1_clkdiv
- 这个实验可以说是verilog入门最基础的实验了，我们不做太多的理论分析，实践是硬道理。 当CPLD的I/O（ FM）为低电平时，三极管导通， 蜂鸣器发声。-This experiment can be said to be the most basic experiments verilog entry, and we do not do a lot of theoretical analysis, practice is the last word. When the CPLD' s
CCD_Verilog_1014
- 基于CPLD器件的线型CCD东芝TCD1501的驱动程序，用verilog语言开发。-CPLD devices based on linear CCD driver Toshiba TCD1501 using Verilog language development.
fpga
- 有关FPGA的好多资料的综合汇总，包括夏宇闻-Verilog经典教程，Verilog-testbench的写法，Altera+FPGA／CPLD设计高级篇，Altera+FPGA／CPLD设计基础篇等好几本书，超值-A comprehensive summary of a lot of information about FPGA, including Xia Wen-Verilog classic tutorial, Verilog-testbench writing, senior Alte
tinycpufiles
- TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程，可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元，外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008)，可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is