搜索资源列表
CPLD-VGA
- 有关verilog的硬件实现VGA设计的代码。
7led
- dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过.
buzz
- dp_xiliux 的 CPLD Verilog设计实验,喇叭演示.代码测试通过.
clock
- dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过.
ledwater
- dp_xiliux 的 CPLD Verilog设计实验,流水灯演示.代码测试通过.
rs232
- dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过.
traffic
- dp_xiliux 的 CPLD Verilog设计实验,交通灯演示.代码测试通过.
CPLD读取ADS7886
- CPLD读取Ti串行ADC芯片ADSL7886的Verilog代码
HPI.rar
- 基于CPLD/FPGA器件的HPI接口程序 难能可贵,HPI based on CPLD/FPGA instrument
div.rar
- 除法器实验 verilog CPLD EPM1270 源代码,Experimental divider verilog CPLDEPM1270 source code
Libra_ps2key_lcd.rar
- 用Verilog语言实现的PS2小键盘输入和1602 LCD显示的功能。无需修改,已经调试通过了。直接可以当成一个模块用于FPGA/CPLD系统开发过程。 这个代码是我在Libra环境下开发Actel FPGA时写的。,Verilog language using the PS2 keyboard and a small 1602 LCD display features. No changes have been adopted debugging. Directly as a module
SPWM.rar
- 用cpld开发的关于生成spwm波的vhdl程序代码,Cpld developed by spwm waves on the generation of vhdl code
adc0804_new.rar
- AD0804驱动,使用新的查表方式,可大大的降低数值运算,节省CPLD的资源,AD0804 driver,using a new method_look up table,which can save a lot of resources of CPLD
mcpu_1.06b
- MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source
MULT
- 乘法器 verilog CPLD EPM1270 源代码-Multiplier verilog CPLDEPM1270 source code
beep
- 用CPLD驱动扬声器实现音乐的播放,程序是用VERILOG写的,-CPLD driver speakers with music player, the program is written in VERILOG,
mux
- 多路选择器 verilog CPLD EPM1270 源代码-MUX source verilog CPLDEPM1270
8ENCODE
- 8位优先编码器 verilog CPLD EPM1270 源代码-8-bit priority encoder verilog CPLDEPM1270 source code
UART
- 串口实验,很好用,我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
UART
- 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code