搜索资源列表
cpld_bus
- CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.-CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.
wavegenerator_testbench
- 此文件采用了verilog语言在cpld中怎样实现波形发生器，及其验证程序-this document using the Verilog language in the cpld How to achieve waveform generator, and the verification process
Altera_uart_Verilog
- FPGA/CPLD应用,uart的Verilog HDL原码-FPGA / CPLD applications, UART Verilog HDL source
beipin
- 用verilog写的cpld的各种分频程序，希望大家指正，谢谢！-using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!
videofram
- 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
pwm_VerilogHDLV1.1
- 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX ＰＬＵＳ ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
CpldandEepromI2c
- verilog 编写的I2c协议程序，用于cpld读写EEPROM-verilog I2c agreement prepared by the procedures for cpld writable EEPROM
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code q
cpldPWM
- verilog HDL 编写的PWM，是初学CPLD者入门Z资源，epm7128stc100-10-verilog HDL prepared by the PWM, is a novice CPLD Getting Started Z resources, epm7128stc100-10
LCD_AV
- 这是用Verilog语言编写AV型LCD屏的驱动程序CPLD上运行并调试成功的。可用作数字到模拟LCD转换-Verilog language AV-screen LCD driver CPLD debugging and running successful. Can be used to simulate LCD digital conversion
keyscan
- 4×4键盘扫描的verilog 代码,在CPLD板上实现
seg7_8
- fpga cpld verilog hdl 语言 代码程序 数码管 控制
RESOLVER
- 旋变位置信号的监测，cpld verilog-Monitoring resolver position signal, cpld verilog
Verilog_prj
- 特权同学的CPLD学习版 Verilog和VHDL代码。含有仿真文件。-Learning Edition privileged students CPLD Verilog and VHDL code. Contains simulation files.
HL-340_xp
- quartus verilog FPGA/cpld 例程 verilog简单例程-quartus verilog FPGA/cpld verilog simple routine routines
sed
- CPLD数码管程序,详细的7段式数码管程序。-CPLD verilog program
0001_EPM3064最小系统模块_带JTAG_LED_2mm插针
- EMP3064的开发板板，原理图，verilog例子，板子说明，规格书，全套资料(EMP3064 development board, schematics, Verilog examples, board instructions, specifications, a full set of information)
I2Csalve.v
- Modified I2C salve design 1. Asynchronous design: ASIC or FPGA design option 2. 8 bits CSR RW interface: 0~15, address and control 3. PAD not included 4. Altera CPLD verified
xapp386
- SPI Implementation on CPLD
ADC0804
- 控制ADC0804的verilog 代码，cpld/fpga都可以使用，用数码管显示ADC采集的二进制数据。(Control ADC0804 verilog code, cpld / fpga can be used to display the ADC digital tube with the binary data collected.)