搜索资源列表
an294_16x16
- Verilog编写的16x16的可交叉的CPLD程序,可用在16个VGA入,16个VGA输出-16x16 cross switch CPLD software wrote by verilog which can be used in 16 VGA input , 16 VGA output application
FSM-design
- An overview of Finite State Machines. FSMs are an important aspect of FPGA and CPLD desig using VHDL and Verilog-An overview of Finite State Machines. FSMs are an important aspect of FPGA and CPLD desig using VHDL and Verilog
avalon_pwm_module_v2.51_completed
- verilog语言cpld实现多路pwm模块-verilog language cpld multi Road pwm module
EPM240VHDLVERILOG
- 大量的Verilog和vhdl源程序学习cpld好资料-Verilog and vhdl lot of good information source to learn cpld
123
- Verilog是广泛应用的硬件描述语言，可以用在硬件设计流程的建模、综合和模拟等多个阶段。随着硬件设计规模的不断扩大，应用硬件描述语言进行描述的CPLD结构，成为设计专用集成电路和其他集成电路的主流。通过应用Verilog HDL对多功能电子钟的设计，达到对Verilog HDL的理解，同时对CPLD器件进行简要了解。
dac8552
- 使用Verilog HDL语言编写的实现DAC8552的时序程序，单片机总线与CPLD/FPGA通信，单片机负责控制送数实现功能。-Use Verilog HDL language DAC8552 realization of temporal procedures, SCM bus and CPLD/FPGA communication, SCM control to send several functions.
hangci
- verilog写得频率记，专门测频率，在cpld上运行，epm240t1-verilog frequency note written specifically measured frequencies cpld run, epm240t100
paral
- 其实是verilog的关于并行的传输的代码，cpld上用的.-paral port
cpld_10fenpin
- 针对cpld芯片采用verilog编程实现的10分频程序。附带其功能仿真文件。-For cpld chip verilog programming of 10 frequency program. With its functional simulation file.
7duanshumaguandejingtaixianshi
- 采用Verilog语言编写实现7段数码管的静态显示，经过CPLD开发板验证，程序正确-Verilog language used to achieve a static 7-segment display, after a CPLD development board verification, the program correctly
3-8-yimaqi
- 38译码器程序，采用verilog语言编写，在CPLD开发板上经过验证，希望对大家有用-38 decoder program, using verilog language, proven in the CPLD development board, we hope to be useful
juzhenjianpan
- 矩阵键盘程序，采用Verilog语言编写，在CPLD开发板上经过验证，正确无误，希望对大家有用-Matrix Keyboard Program, the use of Verilog language, the CPLD development board verified and correct, we hope to be useful
PWMPLED
- 程序正确无误，采用Verilog语言编写，并在CPLD开发板上经过验证，希望对大家有用-Program is correct, the use of Verilog language, and proven in the CPLD development board, we hope to be useful
chufaqi
- 除法器程序，采用Verilog语言编写，并在CPLD开发板上经过验证，正确无误，希望对大家有用-Divider procedure for the Verilog language, and CPLD development board verified and correct, we hope to be useful
Writing_Testbench
- 是基于CPLD/FPGA的硬件开发环境测试文本编写的优秀书籍，其语法格式更加接近于C，适合入门者使用-verilog is based on CPLD/FPGA hardware descr iption language, its syntax is closer to C, suitable for beginners to use
fengmingqi
- 蜂鸣器程序，采用Verilog语言编写，在CPLD开发板上经过验证，希望对大家有所帮助-Buzzer procedure for the Verilog language, proven in the CPLD development board, we hope to help
Altera-FPGA_CPLD
- FPGA CPLD 高级篇 教你怎么编verilog-FPGA CPLD senior articles teach you how to compile verilog
zidongshouhuoji
- 自动售货机的verilog使用，可以作为初学CPLD的一种参考。-Verilog vending machine use, can be used as a reference for beginners CPLD.