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CPU-card-reference-design-operation
- CPU卡又被称为智能卡，由于其具有很高的数据处理和计算能力以及较大的存储器容量，因此具有较强的应用灵活性和适应性。 本文主要讲述CPU卡操作参考设计！仅供参考-CPU card reference design operation
CPU-IC
- CPU卡一些资料，CPU IC卡系统通讯协议及底层程序的设计，CPU卡详解-CPU card with some information, CPU IC card system communication protocol and the underlying process of design, CPU card Detailed
mips-cpu
- 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
CPU
- 流水式CPU设计，实现在MIPS基础上修改的16位THCO-MIPS指令系统，解决了数据、结构、控制冲突，并实现了软硬中断-Pipelined CPU design, implementation, based on changes in the MIPS 16-bit THCO-MIPS instruction set to address the data structure, control of conflict, and to achieve the hard and soft int
CPU-source-code
- CPU设计代码，包括单周期CPU，多周期CPU，流水线CPU及相关ALU组件。-CPU design code, including single-cycle CPU, multi-cycle CPU, ALU pipeline CPU and related components.
cpu-and-ram
- 这是一个用VHDL语言写的简单带存储器的CPU设计，不涉及流水线设计，只是简单的利用QUARTUES II里的ram-This is a simple memory write VHDL CPU design, does not involve the assembly line design, simply use the ram in QUARTUES II
the-strong-cpu-design
- 增强型CPU设计，带有PC指针与存储器，用VHDL语言写的，不含流水线设计，实现二进制灯循环亮-Enhanced CPU design, with the PC pointer memory write VHDL language, non-pipelined design to achieve binary bright light cycle
RISC-CPU-design
- 16位RISC-CPU设计，高四位为操作码，低12位为地址，寻址空间位4KB。包含12条指令（预设16条指令），3个基本测试文件及其Modelsim仿真结果。-16-bit RISC-CPU design, the high four bits for the opcode, the lower 12 address, the address space of 4KB. Consists of 12 instructions (default 16 instructions), the thre
CPU
- 流水线简单CPU设计，基于简单的数字系统设计，为verilog语言，电路设计基于基本的数字电路-Pipelined CPU design, design of digital system based on a simple, Verilog language, based on the basic digital circuit design
CPU
- CPU设计时间报告，VHDL含有详细代码，下载到实验台后能用-Can be used after the the CPU design time report, VHDL contains detailed code downloaded to the bench
CPU
- 哈尔滨工业大学，计算机专业，计算机设计与实践课程，CPU设计-Harbin Institute of Technology, computer professional, computer design and practical courses, CPU design
cpu-risc
- wb_switch，cpu设计，精简指令cup设计-wb_switch，opencore，risc cpu design。
CPU
- 东南大学VHDL课程CPU设计 Verilog语言-Southeast University, CPU design Verilog language VHDL course
CPU
- 16位单周期CPU设计 重庆大学 计算机组成原理项目-16 single-cycle CPU design Chongqing University of Computer Composition Principle Project
16-CISC-CPU-design
- 16位精简指令集的CPU设计，有完整的步骤和原程序可供学习-16-bit RISC CPU design, complete steps and the original program for learning
cpu
- 8位实验CPU设计利用设计好的指令系统，编写汇编代码，以便测试所有设计的指令及指令涉及的相关功能。设计好测试用的汇编代码后，然后利用Quartus II软件附带的DebugController,编写汇编编译规则。接着，利用DebugController软件把汇编编译之后的二进制代码置入到所采用的存储器中，并对设计好的8位CPU进行测试。-Eight experiments designed CPU design using the instruction set, write assembly
MIPS-and-CPU-design-and-simulation
- 兼容MIPS指令集的CPU设计与仿真 处理器架构为多周期，指令用32为字长（取指占一个周期），4k的存储器（指令存储器和数据存储器分开），IO与存储器统一编制，能支持20条指令以上-MIPS instruction set compatible CPU design and simulation
cpu
- 16位实验CPU设计——设计16位的ALU，实现9种运算：逻辑运算（与、或、非、异或）4种、算术运算（加、减、自加、自减）4种以及传送操作1种；-16 Experimental CPU design
CPU
- 4位精简指令集的cpu设计，是数字电路与逻辑的课程设计，对于学习微处理器和数字电路的同学还是很有帮助的-4 RISC cpu design, digital circuit and logic of curriculum design, microprocessors and digital circuits for learning or helpful for students
CPU
- 经典的CPU设计，内部有详细的资料和设计方案，与PCI8位单片机指令兼容-Classic CPU design, detailed information and internal design, compatible with PCI8 bit microcontroller instruction