搜索资源列表
vhdl_crc
- 在quartus中用VHDL语言开发的crc校验
ultimate_crc.tar
- VHDL语言实现的CRC码程序,可用于FPGA实现
crcvhdl
- vhdl 是想的CRC，本程序已经实现调试-vhdl is to the CRC, the realization of the debugging process has
CRC_16
- crc16的串行和并行写法，而且有详细的测试文件-Serial and parallel crc16 written, and detailed test documents
80300di
- this a vhdl program for crc encoder and decoder-this is a vhdl program for crc encoder and decoder
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
ArbitraryCRC
- crc校验通用你模块，可以设置数据宽度和校验多项式。vhdl语言-crc
crcm
- 基于VHDL的5位经典的CRC校验码, 简单容易学习，-Based on the five classic VHDL CRC check codes, simple and easy to learn,
crcm
- 用VHDL实现的CRC冗余码校验功能，QUARTUSii软件实现的-VHDL implementation of the CRC with the CRC function, QUARTUSii software implementation
VHDL_language_design_of_CRC_incidence_and_validato
- VHDL语言设计的CRC发生和校验器VHDL language design of CRC incidence and validator-VHDL language design of CRC incidence and validator VHDL language design of CRC incidence and validator
communications_1
- 用vhdl代码描述的通信系统仿真程序。包括信源（20位m序列），crc编码（采用串行算法），加噪（用22位m序列产生稀疏的1，然后和编码后的数据异或）。-Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), noise (with 22 m se
communications_2
- 用vhdl代码描述的通信系统仿真程序。包括信源（20位m序列），crc编码（采用串行算法），加噪（用22位m序列产生稀疏的1，然后和编码后的数据异或），crc解码，数据串行输出。 -Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), no
33162769crcm
- 基于FPGA的差错控制编码，CRC循环校验码的VHDL程序代码，含仿真文件-FPGA-based error control coding, CRC cyclic check code VHDL code, including simulation file
CRC_Check
- crc校验的vhdl验证，模块分为编码组帧解帧解码模块-vhdl crc checksum verification, the module is divided into coding frame decoding module framing solution
crc16
- 16位的CRC校验 使用VHDL实现 有几个模块 主模块 接收模块 测试模块-16-bit CRC checksum VHDL implementation
CRC_for_8023
- 基于802.3以太网协议的CRC校验程序，使用VHDL语言，4位数据并行执行-CRC inspection program based on the 802.3 Ethernet protocol, the use of VHDL, four data parallel execution
CRC32
- CRC-32的VHDL程序。处理位宽为32位。-32 CRC-32 VHDL program
crc32
- 8bit并行crc32校验vhdl程序，计算完成后一次读出crc值-8bit parallel crc32 checksum vhdl program，reading out crc after calculating the value
crcserialandparallel
- crc serial and parallel ,vhdl ,quartus 2-crc, serial and parallel, simple vhdl, quartus2
CRC1
- 该文件包括CRC校正的VHDL实现，可计算出校验值，并插入起始和结束帧，在接收端判断错误-The document includes CRC correction of VHDL, calculate checksum and insert the start and end frames at the receiving end of an error of judgment