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Digital.Logic.And.Microprocessor.Design.With.VHDL
- Digital Logic And Microprocessor Design With VHDL
VerilogSynthesis
- 有关Verilog综合方面的教程,挺有用的-(Prentice) Verilog HDL--Guide to Digital Design & Synthesis (2nd.Ed.)
q733
- 双线性变换法设计数字高通和带通滤波器,欢迎分享!-Bilinear transform design digital high-pass and band-pass filters
Digital_Signal_Integrity
- 信号完整性的经典书籍,美国电子工程师德必备之书。认真读完后才能懂得电子设计-Signal integrity of the classic books, the United States and Electronics Engineers Germany must have book. Know how to read only after careful electronic design
IIR
- 用双线性Z变换法设计IIR巴特沃思型数字低通滤波器,能够实现心电信号中随机噪声的去除。-Bilinear Z transform with the design of IIR Butterworth digital low-pass filter, ECG can be achieved in the removal of random noise.
echo1
- Adaptive Echo Canceller Using a Modified LMS Algorithm Abstract –– In this paper, an echo canceller is presented, using an adaptive filter with a modified LMS (Least Mean Square) algorithm, where this modification is achieved coding error on con
fir
- 数字电路设计中的,fir滤波器设计,我做的是8位宽的,利用vhdl实现,附带了完整的代码,报告,我没有对我的信息进行删除,是希望大家能够诚实的利用这个代码,提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information i
FIR
- The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. Th
CPLD_portable_digital_storage_oscilloscope_hardwar
- CPLD的便携式数字存储示波器硬件平台设计-CPLD portable digital storage oscilloscope hardware platform design
stopwatch
- 数字秒表的VHDL代码。当设计文件加载到目标器件后,设计的数字秒表从00-00-00开始计秒。,直到按下停止按键(按键开关S2)。数码管停止计秒。按下开始按键(按键开关S1),数码管继续进行计秒。按下复位按键(核心板上复位键)秒表从00-00-00重新开始计秒。-The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stop
Digital-image-processing-technology
- 数字图像处理技术,通过系统的学习,可以了解图形软件等的设计原理-Digital image processing technology, through systematic study, to learn graphics software design principles
FPGA-DSP-design
- 高速数字信号处理fpga-dsp设计课件,如何设计高性能嵌入式系统。-High-speed digital signal processing fpga-dsp design of courseware, how to design high-performance embedded systems.
jj
- 本题设计一个数字存储示波器,以Xilinx公司20万门FPGA芯片为核心,辅以必要的外围电路(包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块),利用VHDL语言编程,实现了任意波形的单次触发、连续触发和存储回放功能,并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时,将外部输入信号经信号调理模块调节到A/D电路输入范围,经A/D转换后送入FPGA内部的双口RAM进行高速缓存,并将结果通过D/A转换送给通用示波器进行显示,完成了对中、低频信号的实时采样和高频信号的等效采
szdyb-proteus-CODE
- 利用proteus软件设计的数字电压表,包含有原理图和程序代码。-Proteus software design using the digital voltmeter, contains schematic and program code.
VHDL_digital_lock_design
- VHDL课程的源代码数字密码锁的设计与实现的实验报告,内附源代码-VHDL source code for the course digital code lock design and implementation of the experimental report, included the source code
IPTV2
- 当前数字电视中EPG的常用设计方法不适合用来设计IPTV中的EPG。根据IPTV系统的自身特点,本文介绍了一种EPG模块的设计和实现方法。-Current digital TV EPG common design method is not suitable for the design of IPTV in the EPG. IPTV system, according to its own characteristics, this paper presents a EPG module d
Fir
- 窗函数法的Fir数字滤波器设计 Matlab-Window function method of the Fir Digital Filter Design
1234
- 基于 Proteus 的等离子切割机控制系统的仿真设计 本文介绍了 Proteus 软件的特点和功能以及基于 Proteus 进行单片机系统开发的过程。在 Proteus 环境下结合Keil C 对空气等离子切割机的控制系统进行了调试仿真,仿真证明,该系统可 以完成空气等离子切割机的整体控制功能。在 Proteus 环境下完成单片机系统的硬件设计和软件 调试,可以降低设计成本,缩短开发周期,提高效率。-Design and simulation of digital contr
microprocessor
- 一个微处理器的Verilog代码,根据英文书籍《数字设计与架构》中的例子而写,能够运行MIPS指令,能正确执行跳转指令。通过modelsim仿真,含测试代码。-Verilog code for a microprocessor, according to the English book " Digital Design and Architecture" was written in the example, to run MIPS instructions to jump
design
- matlab数字信号处理的好算法,可以对处理数字问题达到简便的效果-a good digital signal processing matlab algorithm can deal with the effect of number of issues to simple