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Single-chip-digital-clock
- 单片机数字钟，实现时分秒的LED显示，以及闹钟功能，起参数可以根据需要自己调，供实验参考-Single-chip digital clock, minutes and seconds to achieve the LED display, and alarm clock function, since their parameters can be adjusted as needed for the test reference
multisim
- 这是多功能数字钟的文档，用Multisim10开发，有原理图以及说明。-This is a multi-functional digital clock document, with Multisim10 development, there is schematic and instructions.
CLOCK
- 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
clock
- EDA 数字钟实现文件 能够实现计时,闹钟,校时功能 -EDA digital clock time to achieve the realization of paper, alarm clock, school functions
clk_vhdl
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
digitalclock
- Verilog数字时钟 实现24小时的监控，用七段码显示出来，包含时序图等 在ISE下仿真-digital clock Verilog
digital-clock-
- 51单片机 制作数字时钟 c语言程序 数码管稳定显示 通过按键可以增加分秒-The 51 MCU production digital clock c language program
digital-clock
- digital clock by verilog
clock
- 很好的多功能数字钟的HDL代码不可多得的哦-Good multi-function digital clock of the HDL code rare Oh
clock
- 这个程序可以用来做数码时钟，也可以用来做定时开关！-This procedure can be used to make the digital clock can also be used to do regularly switch!
shuzidianzizhong
- 此次设计与制做数字钟就是为了了解数字钟的原理，从而学会制作数字钟.而且通过数字钟的制作进一步的了解各种在制作中用到的中小规模集成电路的作用及实用方法.且由于数字钟包括组合逻辑电路和时叙电路.通过它可以进一步学习与掌握各种组合逻辑电路与时序电路的原理与使用方法.-Design and production of the digital clock digital clock in order to understand the principle, so learn to create digit
clock
- 用高速硬件语言VHDL设计的全功能数字钟，经测试运行稳定-VHDL language used high-speed hardware design full-function digital clock, tested and stable operation
MCU_Digital_Clock
- <基于单片机的数字钟设计> 个人做的毕业设计,带Protel图,源代码用proteus软件仿真通过,附有毕设论文-<Based on single-chip digital clock design> individuals do graduate design, with Protel map, the source code through the use of Proteus software simulation, complete with paper-ba
Digital_Clock
- 使用汇编语言实现数字时钟设计，用7seg完成显示，并可以通过button对时钟进行调整。并包括系统仿真原理图，适合做设计者使用-The use of assembly language to achieve digital clock design, with the completion of 7seg show, and can adjust the button on the clock. And includes system simulation schematic diagram,
CL
- 数字时钟程序 DOS ASM 汇编语言-Digital Clock procedures DOS ASM assembly language
DigitClock2
- 本工程通过vc++6.0实现了数码管的显示 可以显示漂亮的数字时钟显示-This works through vc++ 6.0 to achieve a digital tube display can show beautiful digital clock display
digitalclock
- This document gives a project with title digital clock using labview.
vhdl-digital
- VHD L数字钟 设计源码 包括 设计思想 设计模块 -VHD L source, including digital clock design design design module
VHDL Digital Clock
- A digital stop watch designed in VHDL
1300551238_28620_FT0_digi-clock
- Embedded Schematic digital clock circuit design