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clock
- 用verilog实现的数字跑表,下载到FPGA开发板上验证通过。下载后从新分配引脚即可用。-Verilog implementation using digital stopwatch, download to FPGA development board to verify the adoption. After the download you can use the new distribution of pins.
clock
- 软件开发环境:ISE 7.1i 仿真环境:ModelSim SE 6.0 1. 多功能数字钟-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock
clock
- 数字钟是采用数字电路实现“时”、“分”、“秒”数字显示的计时装置。由于数字集成电路的发展和石英晶体震荡器的使用,使得数字钟的精度、稳定度远远超过了机械钟表,已成为人们日常生活中必不可少的必需品。-Digital Clock is a digital circuit implementation, " when" , " sub" , " second" The figures show that the timing device. Digita
clock
- This the source code of a digital clock implemented using Atmel 8 bit AVR Controller(ATMega16). To fully understand it look at the hardware implementation shown in attached photo(pdf).-This is the source code of a digital clock implemented using Atme
clock
- 本文档采用VHDL语言编写了一个数字时钟的程序,该数字时钟采用24小时制计时,可以实现整点报时,时间设置,闹钟等功能。最小分辨率为1秒。-VHDL language in this document using a digital clock to prepare the procedure, the digital clock 24-hour time system, you can bring the whole point of time, time settings, alarm clo
Digital_clock
- Qt实现的一个数字时钟,是一个dll,运行bat就可以生成工程文件,调试的时候可以改成EXE程序-Qt to achieve a digital clock is a dll, run the bat can be generated on the project file, when debugging process can be altered into EXE
vhdl-clock
- 数字时钟的VHDL课程设计 涉及到的几个要点有 分频模块 时分秒模块 扫描模块 显示模块-Digital Clock Design of VHDL course of a few key points related to one of those who every minute frequency module module module module scan
Clock
- 一个win32写的汇编程序,里面的功能很强大,有着很好的界面支撑(包括数字钟和指针型的圆盘钟面),功能特点有:1.可以对时间进行设置2.可以设置界面的透明效果,可以最小化钟面到系统托盘3.可以使窗口中在最前面4.可以改变钟面的颜色5.可以定时,设定闹钟时间和闹钟铃声6.有相应的帮助操作chm(即支持chm帮助文件)7.其中的数字钟是用我的图像做钟面的,喜欢的人请不是随便抄袭和改变。 希望大家喜欢,共同进步!-A compilation of written procedures for
digital_clock_design
- 利用VHDL语言,逻辑器件设计CPLD,实现数字钟-Using VHDL language, design of logic devices CPLD, digital clock
clock
- 12864三按键的液晶数字钟,c语言源代码-12864 c button LCD digital clock, c language source code
1632driver
- 是一种显示驱动器,它广泛应用在数字时钟、温度计、湿度计等工业仪器仪表显示中。 步行小绿人是利用驱动由个×点阵块组成的×点阵幕来显示小緑人行走动画。采为主芯片来控制进行数据传输,通过三根线数据写入。 有两种显示方式:此设计采用显示方式。 步行小绿人由幅不同姿势的画面来完成一个走路动作。按键用来改变小绿人动作状态。 - is a display driver, it is widely used
clock-mega8_4bit-7se
- 4位7段数码管电子钟C语言源文件,使用ICC开发,单片机为ATmega8,详细接口定义见注释-4-digit 7-segment digital tube digital clock C language source files, use the ICC development of SCM as ATmega8, detailed interface definitions, see note
MCU_Digital_Clock
- 单片机的数字钟设计,毕业设计,带Protel图,源代码用proteus软件仿真通过,附有毕设论文-Microcontroller digital clock design, graduate design with Protel map, the source code through the use proteus software simulation, with a Bi-based papers
digitalwatch
- Describe: This VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The e
shuzizhong1main
- MSP430单片机中数字钟模块的参考程序,直接可以使用,调试通过,性能良好-MSP430 MCU digital clock module reference program can be used directly, debugging passed, good performance
7SegmentDigitalClock
- LABVIEW开发的。分7段的LEN时钟显示,希望对你有帮助.-this is labview 7 Segment Digital Clock.
digital-clock
- 该数字钟论文是我用了一周的时间,采用Verilog DHL语言设计, Quratuse8.1仿真通过的文章-This paper is a digital clock I used a week, Verilog by DHL language design, Quratuse8.1 simulation through the article
0608190248xiatao
- 实验利借助于Quartus II 软件设计了一个多功能数字钟,实现了校时,校分,清零,保持和整点报时等多种基本功能,此外还实现了闹钟,星期,音乐闹铃等附加功能。本文首先利用Quartus II进行原理图设计并仿真调试,最后在实验板上验证了设计的正确性。 关键字:数字钟 闹钟 仿真 准点报时 -Quartus II software by means of experimental Lee designed a multi-functional digital clock and real
clock
- verilog数字钟 Verilog HDL 写的不是很好,有好的就不要下我的了-verilog clock
Digital-Clock-Countdown-Timer
- Digital Clock Countdown Timer