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firelogd-1.3
- Firewall Log Daemon是一个用C编写的程序，它实时监视IP链或IP表日志警告。程序将启动一个小型后台监控进程，通过读取由系统日志写的FIFO来分析和解决防火墙日志。它可以查询一批警告，并将它们用邮件发送给你，或是由一个脚本用来处理现存的日志文件或数据流。它的功能有主机名，端口，协议，和ICMP类型/代码检查，可以由用户定义模板来格式化输出-Firewall Log daemon is a C preparation procedures, which real-time moni
页面置换
- 页面置换算法的演示程序及代码，包含FIFO、LRU、OPT算法-pages replacement algorithm code and demo program, including FIFO, the LRU, OPT algorithm
fifo_VHDL
- 该文件是先入先出fifo的源代码和测试文件-the document is first-in-first out fifo the source code and test document
fifo_lru_opt
- 操作系统课程设计，页面置换算法，包含了先进先出fifo、最近最久未使用lru、还有最佳opt三种算法。代码简单易懂，编译通过。-courses on operating system design, page replacement algorithms, including the FIFO fifo. the most recent time on the use of LRU, the three best opt algorithm. Code straightforward compi
EZW_example
- EZW举例 该源代码包含有6个文件： EZW.H － EZW编码器头文件 EZW.C － EZW编码器文件 MATRIX2D.H MATRIX2D.C － 编码器数据结果定义和数据操作 FIFO.H FIFO.C － 扫描方式定义：先入先出原则 LIST.H LIST.C － 零树结构定义和操作 UNEZW.C － EZW解码器-EZW For the source code contains six documents : EZW.H - EZW-header
FX2_Slave_FIFO
- 68013 Usb2.0芯片Fifo驱动驱动程序源代码-68,013 Usb2.0 SC16CxxBUARTs driver chip driver source code
taotaisuanfa
- 使用Microsoft Visual C++ 6.0编写最佳（Optimal）淘汰算法、先进先出（FIFO）淘汰算法、最近最久未使用（LRU）淘汰算法的源代码-using Microsoft Visual C 6.0 to prepare the best (Optimal) eliminated algorithm, FIFO (FIFO) eliminated algorithm, the most recent time on the use (LRU) algorithm out of
generic_fifo
- 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
VHDL_Memory_Library_Code
- 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
simple_fifo
- verilog HDL原码 一种简单的同步FIFO原码，可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated
Cache_FIFO
- 模拟内存高速缓存技术C源码，主要是FIFO形式。-simulated high-speed cache memory technology C source code, is the main form of FIFO.
EZWVCcode
- 介绍EZW编解码算法的全部代码，该源代码包含有6个文件： EZW.H － EZW编码器头文件 EZW.C － EZW编码器文件 MATRIX2D.H MATRIX2D.C － 编码器数据结果定义和数据操作 FIFO.H FIFO.C － 扫描方式定义：先入先出原则 LIST.H LIST.C － 零树结构定义和操作 UNEZW.C － EZW解码器 -introduced EZW coding of all the code, the source code incl
vga.niosII.compent.v
- 在cyloneIIFPGA平台下设计完成测试通过的VGA控制器代码。显存留在系统的SDRAM中，用FIFO作为缓冲。-in cyloneIIFPGA platform design is completed tests through the VGA controller code. RAM in the system SDRAM, and use as a FIFO buffer.
os8_2_fifo_ST_Blinky
- ucos_ii在str710f2z6上的移植及串口驱动（包含了fifo）源代码。其中“读我。txt”文件中有移植时做的简单笔记。希望对需要的初学者有所帮助。-ucos_ii str710f2z6 in the transplant and Serial Driver (including the fifo) source code. Which "I read. Txt "file a transplant when so simple notebook. Hope to b
syn_fifo
- 同步FIFO的verilog编码 -synchronous FIFO verilog coding synchronous FIFO verilog Synchronous Code FI FOR the verilog coding synchronous FIFO verilog coding
ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
mp3blaster-3.1.3.tar.tar
- After the single transaction waveforms are implemented in the GPIF Designer, the next step is to integrate the USB portion of the overlying firmware with the GPIF Designer output to perform write and read operations to and from the external FIFO. T
FlashProgramTool
- After the single transaction waveforms are implemented in the GPIF Designer, the next step is to integrate the USB portion of the overlying firmware with the GPIF Designer output to perform write and read operations to and from the external FIFO. T
BMI160 fifo
- 博士BMI160驱动代码，主要包括fifo的使用以及fifo数据获取和解码(Dr. BMI160 driver code, including the use of FIFO, as well as FIFO data acquisition and decoding)
asyn_fifo
- 异步fifo,异步的先进先出，verliog hdl代码，已经经过调试(Asynchronous fifo, asynchronous first out, verliog HDL code, has been debugged)