搜索资源列表
fifo
- fifo的实现，通信集成电路设计的作业，包含模块源程序，源代码，适合初学者。-The realization of FIFO, communication circuit operation,Module design, test vector，source code,Suitable for beginners,Convenient experiment,Very good, right
SLAVE-FIFO-8BITS
- EZUSB FX2 的 SLAVE FIFO例程，包含8051的Firmware以及FPGA的FIFO控制代码 -EZUSB FX2 SLAVE FIFO sample program, including the 8051 firmware, and 8-bit VHDL slave FIFO interface code for FPGA
FIFO-simplify-0227
- DSP2812 与上位机通讯FIFO堆栈模式源代码-DSP2812 and PC communication FIFO stack mode source code
fifo
- FIFO缓存器的设计及VHDL测试平台代码-FIFO buffer design and VHDL testbench code
FIFO
- This a simple example of FIFO(first in and first out) module written in verilog code-This is a simple example of FIFO (first in and first out) module written in verilog code
xfft_v3_2_pipe_64
- vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband-vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband
20131010-code
- fx2lp 68013 xilinx XC3s400 实现slave fifo通讯，包括68013的固件以及fpga的代码（verilog）。摸了好久才调试通过的，特共享出来解救苍生！-fx2lp 68013 xilinx XC3s400 slave fifo
FiFo
- 请求页式存储器管理，代码详细，注释清楚，算法简单易懂-Request page memory management code in detail, comments clear, straightforward algorithm
fifo
- 同步FIFO设计一个同步FIFO，该FIFO深度为16，每个存储单元的宽度为8位，要求产生FIFO为空、满、半满、溢出标志。请采用可综合的代码风格进行编程。-Synchronous FIFO design a synchronous FIFO, the FIFO depth is 16, the width of each memory cell is 8, required to generate the FIFO is empty, full, half full, the overflow
OV7670-Camera-Module-with-FIFO
- it is a source code to drive camera
Code
- SIMULATION OF NETWORK TOPOLOGY USING NS2 Consider the network where T1-T6 are transmitters and R1-R6 are receivers. R1 receives from T1, R2 receives from T2 and so on. B1,B2 and B3 act as bottleneck nodes and also provide for routing of packets
FIFO
- 客户进程-服务器通信，用于学习FIFO进程间通信-cilent-sever-FIFO,linux code
fifo
- 异步FIFO实现 verilog代码，利用格雷码消除亚稳态-Asynchronous FIFO realize verilog code, Gray code to eliminate the use of metastable
FIFO.v
- 异步先进先出FIFO存储器，采用格雷码判定，消耗资源更小-Asynchronous FIFO FIFO memory, using Gray code determination, consume less resources
FIFO
- FIFO，先进先出缓冲器，verilog源代码，包括测试代码。-FIFO, FIFO buffer, verilog source code, including test code.
FIFO
- 关于异步FIFO的原码程序，采用格雷码改善了二进制码带来的不足- ON划词翻译ON实时翻译 On asynchronous FIFO the original code procedures, the use of gray code improves deficiency caused by binary code
New_UART_verilog
- 这个是最新的UART的verilog代码，里边含有和UART相关的所有function,比如状态机，接收发送FIFO等相关代码。-New UART verilog sample code,Include FIFO code state mashine code ,recevier/trasmiter code
fifo
- 同步fifo和异步fifo程序，含时钟同步。运用格雷码-Synchronous FIFO and asynchronous FIFO FIFO procedures, including clock synchronization. Application of gray code
SLAVE-FIFO-16BITS
- CY7C68013a的slavefifo的固件源代码，keil编写，以及使用FPGA向EP6端点写数据的verilog源代码，没有错误，可以编译成功!-CY7C68013a of slavefifo firmware source code, keil prepared using FPGA and write data to the endpoint EP6 verilog source code, no errors, you can compile successfully!
grey-code--FIFO-IP-core
- 基于格雷码的FIFO的IP核，调试可用于通信接口的队列传输。-Gray code based on FIFO IP core, debugging can be used for communication queue transmission interface.