搜索资源列表
VHDL_Memory_Library_Code
- 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
fifo源程序
- fifo源程序，VHDL编写~具有一定的参考价值~-source code of a fifo, writen in VHDL, will be useful to some extent as a reference
fifo
- FIFO 是一种先进先出数据缓存器，这是一个同步FIFO的VHDL源程序，将FIFO分成几个模块进行设计，最后用顶层文件进行模块化设计。-FIFO is a FIFO buffer, which is a synchronous FIFO in VHDL source code, will be divided into several modules FIFO design, top-level files Finally, the modular design.
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
fifo
- first in first out VHDL code
fifo_template
- aes code with fifo control to memory
pgm
- uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
SLAVE_FIFO_16BITS
- 68013和FPGA通信 含有68013 slave firmware 含有FPGA VHDL程序-communication between 68013 and FPGA including 68013 slave firmware including FPGA VHDL code
vhdl-ad9910
- ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to s
Flag-of-asynchronous-FIFO
- Quartus平台，VHDL代码编写的带标志位的异步FIFO。-Quartus platform, VHDL code is written with the sign bit of the asynchronous FIFO.
FIFO
- vhdl code for first in first out
fifo
- This VHDL code for FIFO that is used in a NOC router-This is VHDL code for FIFO that is used in a NOC router
fifo
- fifo buffer in vhdl, first in first out in vhdl, vhdl code
aFifo
- Function : Asynchronous FIFO VHDL CODE
FPGA-FIFO-VHDL
- 这是一个基于FPGA的异步FIFO设计，利用的VHDL硬件描述语言，内容分析清楚，附带完整代码-This is an FPGA-based asynchronous FIFO design, the use of VHDL hardware descr iption language, content analysis, with complete code
SLAVE-FIFO-8BITS
- EZUSB FX2 的 SLAVE FIFO例程，包含8051的Firmware以及FPGA的FIFO控制代码 -EZUSB FX2 SLAVE FIFO sample program, including the 8051 firmware, and 8-bit VHDL slave FIFO interface code for FPGA
fifo
- VHDL code for DATA PATH for performing A=A+3 and A=B+C TO DESIGN AND SIMULATE DATA PATH FOR PERFORMING A=A+3 AND A=B+C USING ONLY ONE ADDER.
FIFO
- vhdl code for FIFO implementation
FIFO
- first input and first output vhdl code
CCD_Array
- Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.