搜索资源列表
PPM
- 对4比特二进制数据进行PPM调制，位宽可修改(PPM modulation for 4 bit binary data)
test_ad_in
- 通过信号源给AD9220传输数据，并通过uart串口在PC上显示输入的数据(he data is transmitted to the AD9220 through the signal source, and the input data is displayed on the PC through the UART serial port.)
DDS1
- 该文件是dds工程，用的是单片机和FPGA开发板组合实现对存储在FPGA中rom里面的波形数据的，调频率（调频范围是1-1MHz），波形在示波器上显示，单片机实现控制字的发送及控制频率，FPGA实现控制字的接收和存储波形数据,输出波形(The file is a DDS project. It is a combination of single chip microcomputer and FPGA development board to realize the amplitude mod
XADC
- xilinx verilog FPGA驱动AD9613 数据采集DEMO程序(Xilinx Verilog FPGA drives AD9613 data acquisition DEMO program.)
fpga_slavefifo2b_verilog
- fpga控制USB接口数据收发，包含verilog 仿真代码和调试工程(fpga control usb3.0, modelsim simulation, verilog language)
uart
- 此上传文件实现的功能就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。 使用的是串口UART协议进行收发数据。(The function of this upload file is to receive data from PC in FPGA and send back the received data.The serial port UART protocol is used to receive and receive data.)
串口通讯
- 利用FPGA 收发串口数据，可与上位机以及其它芯片通信(Using FPGA to send and receive serial data, it can communicate with the host computer and other chips.)
sd_test
- 基于FPGA的SD卡初始化、读写，实现向FPGA写入数据并读取(SD card initialization, reading and writing, with FPGA based)
rtl
- 实现AD7606数据采集，基于xilinx的6系列(Realization of AD7606 data acquisition)
28_ad9226_test
- 此程序完成了的双路数据的采集，通过ad模块将模拟数据转化为12位数字信号，并通过串口发送在pc端的串口助手中显示(This program has completed the acquisition of dual data. Through the ad module, the analog data is converted into 12 bit digital signals and is sent to the serial port assistant at the PC side
ptos
- 八位并行数据转换为串行数据依时钟信号串行输出(Eight bit parallel data to serial data)
Signal
- 基于FPGA的DDS相位累加器，连接至存有波形数据的rom后再接至DA可以输出对应的波形(abcdefghijklmnopqrstuvwxyz)
USB RAW_上位机
- labview usb上位机，通过USB2.0进行数据通讯(LabVIEW USB host computer, data communication through USB2.0)
rdf0244-zc706-pcie-c-2015-4
- 利用FPGA开发板的PCIE接口实现数据的传输和发送。(Using the PCIE interface of FPGA development board to realize data transmission and transmission.)
SRIO_DSP_X1
- xilinx 7 系列fpga与dsp srio数据传输(fpga and dsp communation with srio)
sobel
- 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Ve
TR4_GPIO1_D8M
- 友晶科技的TR4的开发板，接上D8M摄像头的程序 输出的是MIPI解码后的10位数据 内带signaltap仿真结果和连接图(The development board of TR4, the D8M camera program. The output is the 10 bit data after MIPI decoding. include signaltap simulation results and connection diagrams)
A4_Da_Top
- 利用AD、DA和VGA三个外设来实现简易示波器，DA外设发送正弦波给AD外设，AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。(The simple oscilloscope is realized by using AD, DA and VGA peripherals. The DA peripheral sends sine wave to the AD peripheral, and the AD peripheral res
E7_3
- 对基于符号LMS算法的自适应均衡器进行仿真。要求分别进行算法的性能仿真、生成FPGA测试用的输入信号、仿真权值在运算过程中的数据范围(The adaptive equalizer based on the symbol LMS algorithm is simulated. The performance simulation of the algorithm is required, the input signal for FPGA test is generated, and the da
uart
- 电脑端发送数据与FPGA接收数据程序，uart模块，以及一部分项目里包含的其他的程序(Program for sending data from computer and receiving data by FPGA, UART module)