搜索资源列表
4-1-6
- HDB3编码的verilog实现，已在FPGA上实现全部功能。-HDB3 coding verilog implementation in FPGA to achieve full functionality.
HDB3
- 基于FPGA的HDB3编码 利用VHDL实现的源码-The HDB3 code based on FPGA implementation using VHDL source code
linearcode
- 基于FPGA的线性编码解码，verilog设计实现-FPGA-based linear encoding and decoding, verilog design and implementation
f
- 为了解决传统的维特比译码器结构复杂、译码速度慢、消耗资源大的问题，提出一种新型的适用于FPGA特点，路径存储与译码输出并行工作，同步存储路径矢量和状态矢量的译码器设计方案。该设计方案通过仿真验证，译码结果正确，得到编码前的原始码元，速度显著提高，译码器复杂程度明显降低,性能优良。-The convolution code
Array-of-digital-display
- 无论是单片机 DSP还是FPGA 电子领域常用数码管的编码总结在里面了-Both MCU or FPGA DSP digital electronics used in which the coding summary
33162769crcm
- 基于FPGA的差错控制编码，CRC循环校验码的VHDL程序代码，含仿真文件-FPGA-based error control coding, CRC cyclic check code VHDL code, including simulation file
RScoder
- 基于FPGA的RS编码器设计，verilog hdl语言。-RS encoder FPGA-based design, verilog hdl language.
8B10B_decode
- 介绍8b/10b的编码与解码的详细流程，主要是基于FPGA的实现方法-8b/10b encoding and decoding described the detailed process
Good_HDL_Coding
- Xilinx FPGA设计的编码技巧，尤其适用于S6器件和V5、V6器件。-Xilinx FPGA design coding skills, especially for devices and S6 V5, V6 devices.
mach_test_ok
- verilog曼切斯特编码解码的FPGA实现-verilog Manchester encoding and decoding on FPGA
FSK
- FSK调制的VHDL编码的fpga实现，了解信号的FSK处理方法-FSK modulation fpga implementation of VHDL coding, the FSK signal processing methods to understand
sim_master_v4_1
- 在FPGA中实现按键数码管的功能，加入了电平触发、编码处理、改善按键灵敏度-Button in the FPGA digital control functions, adding a level triggered, encrypted, to improve the sensitivity of key
jianpancaomiao
- 经过对系统做需求分析，详细功能设计、编码，模块连接，并利用FPGA实现相应的功能，经过波形仿真、下载调试，验证了设计方案的可行性及实现方法的有效性，基本实现了系统的要求。-Microwave controller system is a utility-type system that includes not only the function of simple operation, but also good effect of cook. According to fixed routi
2011-diansai-E
- 2011年 电赛 E题 简易数字信号传输性能分析仪FPGA信号发生部分 包括m序列，伪随机序列，曼彻斯特编码 程序 和单片机部分程序-2011 CEC E title simple digital signal transmission performance analyzer FPGA signal part of the program and single-chip part of the program
encode
- 实现用FPGA控制编码芯片AHA4013的编码
encoder_Z64_all_rate
- Wimax矩阵的LDPC编码器，已通过modelsim仿真测试，并前在altera的FPGA板上通过测试,码率5/6，可进入代码内部修改参数，支持2/3,3/4其他2个码率，数据吞吐量为700M-Wimax based LDPC encoder, modelsim simulation passed, also passed on altera FPGA board, code rate 5/6, also support 2/3,3/4, throughout 700m
exp4
- 基于fpga的（7,4）循环码编码电路。vhdl代码-（7,4) cyclic code encoding based on fpga
rscorrect
- OFDM中FPGA部分，随机化，信道编码，交织，这里主要介绍了利用RS编码实现的方法-FPGA portion of the OFDM system, randomization, channel coding, interleaving, introduces the use of RS coding method
JointwaveE460
- jointwave公司的h264编码方案，可实现1080P30，运用在FPGA/ASIC设计-jointwave h264 encoding scheme can be realized 1080P30, the use of FPGA/ASIC design
83
- 基于FPGA的83优先编码器源代码，赛林思比赛专用-Based on FPGA 83 priority encoder the source code, and the "special LinSi game