搜索资源列表
CMOS_proj2_RTL
- 用上位机UART控制一个十字路口的交通灯的.v文件。包括testbench在内，可用FPGA cycloneII DE270跑仿真。-traffic lights at a crossroads. V file controlled by PC UART. Including testbench , available FPGA cycloneII DE270 run the simulation.
ps2.tar
- Alter NIOSII Avalon bus ,PS/2 host controller with initialization code. -FPGA proven. This controller support hot plug. Please read reg_file.v for register setting.
mx7821
- 将D/A输出信号连接到A/D的输入，通过FPGA采样模块转换成数字信号。该模块由设计文件mx7821.v完成-The D/A output signal is connected to the input of the A/D, the FPGA module into a digital signal sample. The module is done by design documents mx7821.v
Most-new-VGA-timing-standards
- 最 新 V G A 时 序 标 准，对FPGA编写VGA驱动有帮助-Most new V G A timing standards for the preparation of FPGA VGA driver help
PCIIP-core
- 基于FPGA的PCI ip core 设计源代码，里面包含所有的fifo,状态机源代码，drives 驱动源代码。-“fifo_control.v” Module FIFO_CONTROL includes control logic for single FIFO. It consists of read and write address generation and full, almost full, empty and almost empty status generatio
breathe_led
- 基于FPGA的呼吸灯程序，压缩包含有整个工程，源码在breathe_led\breathe_led.srcs\sources_1\new\breathe_led.v-breathing light program based on FPGA
codes
- 5 simple verilog codes: Arithmetic.v - arithmetic operations on verilog Accumulator.v - 8 bit adder accumulator counterfpga.v - 4 bit up counter w/ fpga code UpDown3.v - 4 bit Up-down counter w/fpga code pattefier.v - pattern/sequence ident
LED
- FPGA 里面的 小练习 ，LED 流水灯的小程序，请下载联系，是.v文件哦-FPGA inside a small practice, LED light water small program, download links are .v file
sha1_v01
- sha1_testbench.v -- Testbench with vectors NIST FIPS 180-2 sha1_exec.v -- Top level sha1 module sha1_round.v -- primitive sha1 round dffhr.v -- generic parameterizable D-flip flop library Performance Analysis Performance equa
test1
- LED驱动实验 打开电源，将led_test.sof下载至FPGA，观察LED1-LED8的亮灯状态是否与设计吻合。- 将test1\led.v、setup.tcl拷入工程目录。 3. 将led.v加入工程并进行综合编译，察看编译报告。从led.v创建符号文件led.bsf。 4. 建立图形设计文件led_test.bdf,放入led模块，添加输出引脚，并命名为led[7..0]，将led输出与输出引脚相连。
DE1_SoC_Audio
- 声音录制、播放的Verilog代码，用于Altera Cyclone V SOC. 写时适配的是DE1-SOC开发板。-Audio recording and playing code for Altera Cyclone V SOC FPGA. Code was designed for DE1-SOC development board, but could be reference for other boards.
sos_module
- 用FPGA实现sos摩尔密码，即输出电平信号短长短。就是有次序的控制输出莫斯密码的“点”，“画”和“间隔”。而 control_module.v 是一个简单的定时触发器，每一段时间都会使能sos_module.v。-Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password,
AD7606URAT
- AD7606 FPGA du chegnxu -AD7606 .V FPGA du chegnxu
5AST
- Arria V SoC FPGA Development Kit Board 硬件设计资料 Orcad 和 Allegro 的资料-Arria V SoC FPGA Development Kit Board hardware design information and Orcad Allegro information
HDB3
- 针对数字基带传输系统中HDB3信号的特点，采用基于FPGA的Verilog HDL语言，实现HDB3数字基带信号的编码器设计,共有插V、插B、单双极性变换模块，最终能在FPGA实现。-For digital baseband transmission system HDB3 signal characteristics, based on FPGA Verilog HDL language, designed to achieve HDB3 encoder digital baseband si
uart
- FPGA的串口通信 v 文件，直接编译就可以串口通信了，波特率9600(FPGA serial communication, V file)