搜索资源列表
RS2322
- verilog 功能:DSP或单片机向FPGA的DPRAM中写入一块数据(最大不超过2K字节,前2个字节为代发送数据长度),然后给出启动信号send_start,本模块自动读出DPRAM中的数据,按设定的波特率将DPRAM中规定的长度的数据发送出去。 接口信号说明: send_start:启动FPGA串行发送脉冲 sys_rst:系统复位脉冲 bps_setup:波特率选择 clk5_714:5.714MHz时钟 char_in:从DPRAM中读出的代发送数据 R
EMIFA-WRITE-AND-READ-WITH-CS
- FPGA EP3C16F484C8N与dsp TM320C6748 EMIFA之间的通信程序-the code of communication between FPGA EP3C16F484C8N and dsp TM320C6748 EMIFA
my_apll_calcoeff
- 在设计锁相环时,二阶环路滤波器的系数设计极为重要,本程序可以用于FPGA设计锁相环时计算所需的参数。-It is important to calculate a tow order loop filter,when designing a phase locked loop.This program can be used in designing a phase locked loop based FPGA or DSP directly.
mulx
- FPGA verilog乘法器 设计 用FPGA中DSP模块实现-FPGA verilog mulx
DDigital_videS
- 配合DSP做的例子,前段视频采集和转换后, 通过切换SRAM中的数据到DPSS后端处理和FPGA采集操作,具有 一般通用性,更重要的是测试代码丰富,加深理解 -Example, with the DSP do to the DPSS back-end processing and FPGA front-end video capture and conversion, by switching the SRAM data acquisition operations, with genera
TestDSPFPGA
- 一个用于DSP和FPGA通讯的测试程序,FPGA用EMIF接口接入-A test program for the DSP and FPGA communication, FPGA with the EMIF interface access
TMS320C6711DandFPGA
- 为满足某捷联导引头上图像辅助末制导系统的需要,设计了以高速浮点DSP芯片TMS320C6711D和现场可编程门阵列FPGA为核心的高性能图像匹配处理平台。文中详述了该系统的软、硬件设计以及各模块的组成和功能,最后通过软硬件联合测试表明,该系统可完全满足图像导引头上处理速度快、存储容量大、实时性强的要求,并具有小型化、低成本和集成度高的优点。 更多还原-In order to meet the demands of image-aided terminal guidance system,a hi
DSP2812_FPGA_driver
- DSP TMS320F2812驱动FPGA源码-DSP TMS320F2812 driver FPGA source
DSP2812SCH
- 这是前面几个FPGA例子的开发板原理图,是DSP&FPGA综合性开发板,供大家参考学习-This is the first few examples of FPGA development board schematics, a comprehensive DSP & FPGA development board, for your reference learning
ADSample_FPGA
- DSP和FPGA协同处理的ad采集程序,包括DSP和FPGA的代码,需要的请下载-DSP and FPGA co-processing of the ad collection procedures, including DSP and FPGA code, you need to download the
DSPPFPGA20050428
- DSP和FPGA的试验箱原理文件,包括原理图,各种程序AD/flash,流水灯,以及电机控制等各种程序,以及必要的实验指导书-Chamber principle of DSP and FPGA files, including schematics, various procedures the AD/flash light water, as well as motor control and other procedures, and, if necessary, experiment in
eva
- 双空间矢量矩阵变换器的DSP程序,DSP型号2812,换流部分的逻辑由FPGA进行运算。-Double space vector matrix converter DSP program, DSP Model 2812 commutation part of the logic by FPGA computing.
Videocfg
- CCS3.3dsp图像处理。tms320c6713+fpga的图像处理平台-CCS dsp image processing. tms320c6713+fpga image processing platform
Papers
- These research papers will help in FPGA based DSP systems design
34
- TD-SCDMA的长期演进TD-LTE。为减轻TD-LTE综测仪开发中调试的复杂性,通过研究分析TD-LTE系统原语,提出了一种基于DSP TMS320C6455和FPGA 5vsx95tff1136(Xilinx)芯片的原语追踪平台。-Long-term evolution of TD-SCDMA, TD-LTE. TD-LTE system primitives through research and analysis in order to reduce the complexity o
paixu
- TD-SCDMA的长期演进TD-LTE。为减轻TD-LTE综测仪开发中调试的复杂性,通过研究分析TD-LTE系统原语,提出了一种基于DSP TMS320C6455和FPGA 5vsx95tff1136(Xilinx)芯片的原语追踪平台。-Long-term evolution of TD-SCDMA, TD-LTE. TD-LTE system primitives through research and analysis in order to reduce the complexity o
maopao
- TD-SCDMA的长期演进TD-LTE。为减轻TD-LTE综测仪开发中调试的复杂性,通过研究分析TD-LTE系统原语,提出了一种基于DSP TMS320C6455和FPGA 5vsx95tff1136(Xilinx)芯片的原语追踪平台。-Long-term evolution of TD-SCDMA, TD-LTE. TD-LTE system primitives through research and analysis in order to reduce the complexity o
paixufahanshu
- TD-SCDMA的长期演进TD-LTE。为减轻TD-LTE综测仪开发中调试的复杂性,通过研究分析TD-LTE系统原语,提出了一种基于DSP TMS320C6455和FPGA 5vsx95tff1136(Xilinx)芯片的原语追踪平台。-Long-term evolution of TD-SCDMA, TD-LTE. TD-LTE system primitives through research and analysis in order to reduce the complexity o
sushu1
- TD-SCDMA的长期演进TD-LTE。为减轻TD-LTE综测仪开发中调试的复杂性,通过研究分析TD-LTE系统原语,提出了一种基于DSP TMS320C6455和FPGA 5vsx95tff1136(Xilinx)芯片的原语追踪平台。-Long-term evolution of TD-SCDMA, TD-LTE. TD-LTE system primitives through research and analysis in order to reduce the complexity o
Audio-Analysis
- 基于DSP和FPGA的音频信号分析,是全国大学生电子大赛的一等奖作品。含有完整的分析,设计,原理图,器件选择,源代码。-Audio DSP and FPGA-based signal analysis, the first prize of the National Undergraduate Electronic contest works. Containing complete the analysis, design, schematics, device selection, and