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eetop.cn_emif_brg
- fpga与DSP通过emif接口通信，fpga内部通过fifo进行数据缓存-fpga with the DSP through emif interface communication, fpga internal data cache by fifo
Robust and Optimal Control by Kemin Zhou
- Embeded-SCM Develop ARM-PowerPC-ColdFire-MIPS Embeded Linux SCM VxWorks uCOS DSP program Windows CE VHDL-FPGA-Verilog Other Embeded program
test3
- 中断闪灯（CPLD）文件夹中为FPGA部分程序，中断闪灯（DSP）文件夹中为DSP部分程序。中断闪灯（CPLD）中主要是提供DSP工作中所需要的相关信号。在中断闪灯（DSP）中主要实现外部的开关按钮S1的触发产生中断，DSP接收到相关中断信号后，跳转到闪灯子程序中，指示灯HL4开始闪烁。-Interrupt flash (CPLD) folder for FPGA part of the program to interrupt flash (DSP) folder for the DSP pa
a_vhd_16550_uart_latest.tar
- vhdl-fpga-c++-c-wireless networks-linux-verilog-cpld-arm-dsp
echo_dj
- verilog写的回波抵消程序，相当于写了个回波抵消的芯片，不是dsp，可编译后下载于FPGA,绝对原创，写了很长时间。-Verilog echo canceller written procedures, wrote the equivalent of echo canceller chip, not dsp, can be downloaded from the compiled FPGA, absolute originality, writing for a long time. -
FA161-SCH
- 联华众科FPGA开发板FA161核心器件为 Altera Cyclone系列FPGA EP1C6，FA161板载有SDRAM，SRAM，FLASH方便制作各种应用，开发板所带资料中包括了上位机与开发板USB通信，上位机与开发板以太网通信，上位机与开发板串口通信例程。FA161板载有USB 1.1，USB 2.0(CY7C68013A)接口，以太网接口(RTL8019AS)。FA161上可以进行HDL程序开发，可以进行nios ii程序开发，可以结合MATLAB制作DSP Builder应用。FA
dspafpga
- dsp与fpga通信的verilog程序，强烈推荐欢迎参考-dsp and fpga verilog communication program, it is strongly recommended to welcome reference
dspzhongduan
- dsp 与fpga通通过中断交换数据的dsp程序C语言编写，非常完整，编译通过下载即用-dsp and fpga through exchanging data via interrupt dsp procedures C language, very complete, the compiler that is used by downloading
mcbsp_1_14
- DSP的McBsp接口的实现，不过是作为DSP的从机-The realization of McBsp interface of DSP,But the Base is the FPGA as a slaver.
PG1000_EXP3_DSP
- 联合FPGA和DSP的工程文件，可联合调用，实现电压信号的采集处理，并显示在液晶屏上-Joint FPGA and DSP engineering documents, can be combined call to achieve voltage signal acquisition and processing, and display on the LCD screen
FPGASPI
- FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信-FPGA SPI Timing interpretation covering all main modules communicate with the DSP
myuart
- 使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and
CMI
- 传号反转码CMI的实现，包含FPGA和DSP两部分的完整工程-CMI Code Mark Inversion of implementation, including FPGA and DSP two parts of the complete works
c6701
- 航空板上TMS320C6701 DSP配置EMIF，读写SDRAM FLASH 和FPGA等外围电路的源码-Aviation board TMS320C6701 DSP configuration EMIF, literacy SDRAM FLASH and FPGA source code and other peripheral circuits
exercise3
- 用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul
emif_tt
- 实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d-Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding
fpga2dsp
- Altera Stratix II FPGA与TS201 DSP通过链路口通信的程序-Altera Stratix II FPGA and TS201 DSP through a chain junction communication procedures
fpga_ver
- Altera StratixII FPGA与DSP TS201实现总线通信的程序，Verilog实现-Altera StratixII FPGA and DSP TS201 implement the bus communication procedures, Verilog realization
emifa_ram
- FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序-FPGA and DSP EMIF communication
FPGA2-DSP2-EDMA
- 例程是FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者-Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners