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XDS100v3-Design-Kit-1.0-Setup
- 压缩包是ti xds100v3 Design kit的安装文件，安装后有原理图、PCB文件，与DSP接口采用FPGA，安装后有源码，是VHDL格式的，支持开源，降低开发成本-Compression package is ti xds100v3 Design kit installation file after installation schematics, PCB files, and DSP interface with FPGA, after installation source is
EMIF
- EMIF接口调试代码，使用的是Verilog语言，FPGA与DSP通信，测试成功-EMIF interface debugging code that USES the Verilog language, FPGA and DSP communication, testing success
Blink_6713
- DSP6713的LED闪烁程序，包括FPGA的接口程序，DSP与FPGA协同工作。-DSP6713 LED flashing procedure, including the FPGA interface program, DSP and FPGA to work together.
ExternalInterrupt_test
- DSP6713的中断测试程序，包括FPGA的接口程序，DSP与FPGA协同工作。-DSP6713 interrupt testing procedures, including the FPGA interface program, DSP and FPGA to work together.
TIMER_test
- DSP6713的定时器测试程序，包括FPGA的接口程序，DSP与FPGA协同工作。-DSP6713 timer test program, including the FPGA interface program, DSP and FPGA to work together.
PLL_test
- DSP6713的PLL测试程序，包括FPGA的接口程序，DSP与FPGA协同工作。-DSP6713 PLL test procedures, including the FPGA interface program, DSP and FPGA to work together.
SDRAM_test
- DSP6713的存储器测试程序，包括FPGA的接口程序，DSP与FPGA协同工作。-DSP6713 memory test program, including the FPGA interface program, DSP and FPGA to work together.
FPGA_emif
- 接口模块，通过对高位地址的编码可实现在一个FPGA中配置四个独立的功能模块，每个功能模块具有一个带FIFO的输出口和13个独立的可由DSP读写的寄存器，寄存器功能可自定义。模块还包含两个全局寄存器，可实现全局复位，中断等功能。该模块以应用于实际的项目中，目前运行良好-FPGA to emif
AD-and-DA-in-DSPPFPGA
- 上海志宇DSP+FPGA开发板AD/DA回放程序-AD/DA in DSP+FPGA
FLASH_test
- 基于上海志宇DSP+FPGA开发板的FLASH程序开发-FLSAH verilog
data_inout_port
- FPGA的I/O接口方向控制的设计，主要应用于与DSP/CPU等接口。-FPGA s I/O interface design direction control, mainly used in the DSP/CPU and other interfaces.
dsp_link_tx16
- FPGA到TS201的link_port接口，以16位的数据格式传输到DSP。-FPGA to TS201 s link_port interface, 16-bit data format for transmission to the DSP.
DSP28335-bujindianji
- DSP(TMS320F28335) + FPGA(XC3S500E) 控制步进电机例程源代码、原理图-DSP+ FPGA (TMS320F28335) (XC3S500E) control stepping motor example source code and schematic diagram
fifo
- CAN总线，DSP+FPGA+SJA1000架构，FPGA负责逻辑设计,此文件内有FPGA负责dsp和sja1000通信-CAN bus, DSP+ FPGA+ SJA1000 architecture, FPGA logic is responsible for the design, FPGA is responsible in this document have dsp and sja1000 Communications
51--AVR--MSP430--PIC--STM8--STM32
- 各种单片机(51、AVR、MSP430、PIC、STM8、STM32)、ARM、DSP、TFT彩屏、C语言，WiFi小车，FPGA、LINUX、机器人,CAD、VB、Protel99、Protues、Unix、UCOSII等各种视频教程超800G-Various microcontroller (51, AVR, MSP430, PIC, STM8, STM32), ARM, DSP, TFT color screen, C language, WiFi car, FPGA, LINUX, ro
xCORE-200-XU_PB(1.0)
- xcore 电路原理图，集cpu dsp fpga一体，非常好的芯片。-Xcore schematic, set DSP FPGA CPU one, very good chip.
HAPF_SLAVE2
- 高压链式SVG控制用FPGA的verilog程序,其中包括SPI，16路SCI同步通讯模块程序，保护自锁功能程序，基于滞环的无功功率检测和补偿策略；还包括FPGA和DSP之间通过总线方式进行数据的快速交互等；程序完整-SVG high voltage chain of verilog FPGA control procedures, including SPI, 16 road SCI synchronous communication module procedures to protect
FIFO_POLL
- DSP通过EMIF接口访问FPGA内部寄存器（FD6713开发板）-DSP access the internal registers in FPGA via EMIF interface (FD6713 Development Board)
REGISTER
- DSP通过EMIF接口访问FPGA内部寄存器（FD6713开发板）-DSP access the internal registers in FPGA via EMIF interface (FD6713 Development Board)
Updata(2014.07.04)
- dsp和FPGA程序下载，界面用VB编写，重点OUT文件转BIN,FPGA文件转BIN-dsp program download interface and document conversion OUT