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Test_LED[1]
- 用VHDL实现的一个工程，可以参考来学习FPGA的设计-VHDL achieved with a project, you can reference to learn the design of FPGA
VGAVesaDdc_pinout_files
- vhdl code for using lcd in an fpga project
db15-vga-pinout_files
- vhdl code for using lcd in a fpga project
B_to_D
- 二进制转BCD码程序，可作为7段数码管显示的编解码程序，VHDL编写的FPGA工程。-BCD binary code change process, as 7 digital display codec process, VHDL FPGA project prepared.
SIREN
- An Alarm Project Writen in VHDL for FPGA Devices
jishuqi
- 计步器程序 使用vhdl描述 实现实时的计步功能 用fpga实现已通过-step counter Pedometer programs use VHDL achieve real-time project described in step function already through fpga realizing
decoder
- mp3译码器的实现，在fpga上实现多媒体功能-this project is the mp3 decoder， designed by vhdl
bch-coding
- In this project, we are implementing the error detection and correction using BCH code (Bose Chaudhuri Hocquenghem). Using VHDL and targeted on FPGA for synthesis of the code. The encoder and decoder combine called as a codec.
PS2-keyboard
- fpga的ps2-键盘数码管显示程序，包括vhdl，顶层文件，工程文件-fpga of ps2-keyboard digital tube display program, including vhdl, top-level files, project files
zzlB
- QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。-the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing.
AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
pinlvji
- 用VHDL语言编写的频率计，在FPGA上使用，已验证，全工程文件-In the frequency of the VHDL language, on the FPGA has been verified, the whole project file
clock
- vhdl语言实现的时钟功能的quartus工程。在FPGA上运行可以得到时钟效果，并有调节功能。-vhdl language to achieve clock quartus project. Can get the clock running on the FPGA results, and regulatory function.
VHDL-projects
- I have simple five VHDL projects. I use FPGA Spartan3A family board with XC3S50A FPGA chip. This project was created in Xilinx ISE Design Suite version (13.2).It contains divider,XOR blocks, counters, moore automat and more.
vending-machine-project
- vending machine VHDL FPGA Altera
calculator-project-VHDL-FPGA
- Calculator PROJECT FPGA ALTERA DE-2
MY 80c51 IP
- verilog和vhdl混写的工程 内含mc8051软核及最小系统 经测试已调通(Verilog and VHDL mixed with the project, including the mc8051 soft core and the smallest system, the test has been transferred)
LwIP_repo
- Vivado repository for base project for LWIP throughput
rs232
- 使用VHDL语言在vivado平台上编的串口通信的完整工程，并能用EGO1开发板成功验证(The complete project of serial communication is compiled on the vivado platform using VHDL language, and it can be successfully verified with the EGO1 development board.)
ppm
- 使用fpga达成的最短脉冲检测、窄脉冲成型模块程序，语言为vhdl，可用于ppm调制与解调项目设计(The program of the shortest pulse detection based on FPGA is VHDL, which can be used in PPM modulation and demodulation project design)