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UART_VERILOG
- 该程序实现在ALTERA FPGA 上使用VERILOG HDL语言实现串口通信。-The program in ALTERA FPGA VERILOG HDL language used on serial communication.
tlc549adc
- 本程序是用Verilog HDL 状态机编写的tlc549的驱动程序-This procedure is used to write Verilog HDL state machine driver tlc549
uart_verilog
- Verilog HDL语言编写的uart程序，在别人基础上改动和优化完成，quartus ii 10.0编译通过，可综合，板上仿真通过。将PC机发送的字符串发送回，可一次发送多个字符串。-Verilog HDL language uart program, in others on the basis of changes and optimization is complete, quartus ii 10.0 compiler, integrated, on-board through si
smg_8
- 基于verilog HDL预言的8段数码管驱动程序，模块化-Predictions based on verilog HDL 8 digital tube driver, modular
21_ds1302
- 基于verilog HDL语言的模块程序，用于驱动ds1302时钟芯片-Based on verilog HDL language module program for driving ds1302 clock chip
spi_stm32
- 本程序使用verilog hdl 语言编写的SPI程序，可与stm32进行数据的传输-This program uses SPI verilog hdl language program with stm32 for data transmission
keyqudou
- fpga verilog hdl 设计键盘去抖动程序，设计环境quartusii 9.0。仿真绝对通过。-fpga verilog hdl design keyboard to jitter program design environment quartusii 9.0. Simulation absolutely pass.
KEY
- fpga cpld 程序 key 按键 按键检测 verilog hdl
beep
- fpga cpld verilog hdl 语言 代码程序 beep 控制
CPLD_LED
- fpga cpld verilog hdl 语言 代码程序 led 控制
I2C
- fpga cpld verilog hdl 语言 代码程序 beep 控制
switch
- fpga cpld verilog hdl 语言 代码程序 开关 控制
seg7_8
- fpga cpld verilog hdl 语言 代码程序 数码管 控制
Ex21_HDL2
- verilog语言写的TMS320F2812的片外地址分配程序-the CS signal used to distribule CHIP out address by verilog HDL
Regfile
- 利用Xilinx ISE14.3，用Verilog HDL 语言编写的计算器与寄存器堆程序，在Spartan Ⅲ板上调试通过。-Use Xilinx ISE14.3, using Verilog HDL language of computers and register file program, Spartan Ⅲ board through debugging.
verilog_lcd
- 在Quartus ii 环境中实现了LCD模块的控制功能，程序由verilog hdl 语言描述，经测试，该模块功能与预期一致。-In Quartus ii environment to achieve the control functions of the LCD module, the program described by the verilog hdl language, tested, this module functions in line with expectations.
verilog_ps2
- 在Quartus ii 环境中实现了PS2模块的控制功能，程序由verilog hdl 语言描述，经测试，该模块功能与预期一致。-In Quartus ii environment to achieve the PS2 module control functions, procedures described by the verilog hdl language, tested, this module functions in line with expectations.
uart
- 基于FPGA的UART程序设计，VERILOG HDL语言编写，可实现串口通信，波特率为115200。已通过串口调试助手验证。-FPGA-based UART program design, VERILOG HDL language, enabling serial communication baud rate to 115200. Has been verified through the serial debugging assistant.
Oscilloscope
- 开发板上芯片是cycloneII，利用Verilog HDL语言编写程序，将波形和波形数据显示在2.4寸TFT液晶屏上。在开发板上成功实现。-Development board chip is cycloneII, use of Verilog HDL language programming, the waveform and waveform data is shown in 2.4-inch TFT LCD screen. Successful implementation of the
qiangdaqi
- 本程序为四路抢答器verlog HDL语言工程实例。-This program is four Responder verlog HDL language engineering examples.