搜索资源列表
vga-veriloghdl
- 用Verilog HDL编写的VGA显示驱动程序-大家共同学习-Prepared using Verilog HDL VGA display driver- we learn together
PWM
- 应用verilog.HDL编写的PWM波的生成程序-Generation of application of verilog.HDL to prepare PWM wave
counter
- 采用VERIlOG HDL语言设计的一个加法器项目，简单可靠，并把其中测试平台程序加入其中-VERIlOG HDL language designed using an adder project, simple, reliable, and to join the program in which the test platform
MPPT-source-code-based-on-FPGA
- 用Verilog Hdl语言实现的光伏系统最大功率跟踪的源代码，内包含程序解释说明。-Use Verilog Hdl language implementation of photovoltaic maximum power tracking system source code, contained within the program descr iption .
Key_detect_code_based_Verilog
- 用Verilog hdl 语言编写的键盘检测驱动程序-Use Verilog HDL language programme keyboard test driver.
PS_interface_keyboard_driver
- 基于Verilog hdl的ps接口的键盘驱动程序。-Ps interface based on Verilog HDL keyboard driver.
ds1302_drive_program
- 基于Verilog hdl的ds1302芯片的驱动程序-Ds1302 chip driver programme based on Verilog HDL.
Tetris_1
- verilog HDL编写的俄罗斯方块程序，包含游戏控制，得分统计，VGA，PS2键盘控制等模块-verilog HDL Tetris program, including game control, Won, VGA, PS2 keyboard control modules
PLI-example
- PLI是实现C程序和硬件语言，包括VHDL，verilog混合编程的接口规范，本例给出VC++环境示范例子，实现VERILOG可以调用C语言函数。-PLI is the specification to perform interface between C and HDL language. This example give a c function called by verilog!
serial_detected
- 序列产生与检测程序，即通过程序产生一段序列，然后检测到目标序列。verilog HDL-Sequence generation and detection procedures, i.e., a sequence generated by the program, and then detecting the target sequence. verilog HDL
run
- verilog HDL PARTAN 3E100的流水灯程序-verilog HDL PARTAN 3E100 water light program
stopwatch
- FPGA程序，verilog HDL语言编写的秒表程序，使用quartus II 13.0 开发，初学verilog HDL的同学可以参考下-FPGA procedures, verilog HDL language stopwatch program, developed using quartus II 13.0, verilog HDL beginner students can refer
FPGA_Uart
- FPGA程序，verilog HDL语言编写，包含AD转换和串口发送程序，由于AD芯片种类繁多时序迥异，故主要参考串口发送程序。本程序使用quartus ii 13.0 编写。-FPGA procedures, verilog HDL language, includes an AD converter and serial transmission program, since a wide range of AD chip timing are different, so the main
FPGA_cymometer
- FPGA程序，verilog HDL语言编写，提供了一种频率计的实现方式，开发环境为Quartus ii 13.0，初学verilog HDL语言的同学可以参考下-FPGA procedures, verilog HDL language, provides a way to achieve a frequency meter, development environment for Quartus ii 13.0, beginner verilog HDL language students
dacontrol
- 数字量转成模拟量的基于verilg hdl 语言编写的程序 非常好用-digital convert to analog
player
- 这是我利用Verilog hdl语言写的关于音乐播放器的程序，其中还包括了仿真结果，该播放器播放的是梁祝，希望对学习Verilog hdl的同学有所帮助-This is what I use Verilog hdl language program written on the music player, which also includes the simulation results, the player is Butterfly, I hope to learn Verilog hdl
verilog8B10B
- verilog HDL语言实现的8B10B程序，经过仿真可运行-8B10B verilog HDL language of the program, through simulation can be run
watch_dog
- 看门狗程序设计，使用verilog HDL语言编写-Watchdog program design, using verilog HDL language
turbo_encode
- turbo码的编码程序,verilog HDL,在ISE环境中-turbo code encoding process
Float_add
- 该源码利用Verilog HDL语言成功实现了浮点数的加法运算，包括全部工程以及Verilog 源码，经验证，该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful