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iir_filters
- 说明：这个代码是基于FPGA的数字IIR无限长冲激响应滤波器的源代码．-Note : This code is based on the number of FPGA IIR infinite impulse response filter the source code.
IIR_filter_FPGA
- IIR数字滤波器的FPGA实现(图),初学者适用
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- 基于FPGA的IIR数字滤波器的快捷设计 基于FPGA的IIR数字滤波器的快捷设计-FPGA-based IIR digital filter design shortcut FPGA-based IIR digital filter design of fast
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- 各种IIR及FIR数字滤波器的FPGA算法实验指导，适合新手学习。-A variety of IIR and FIR digital filter FPGA-algorithm experimental guide, suitable for novice to learn.
lvbofangfa
- 针对全数字软件接收机中抽取滤波器的设计,提出了一种适合在FPGA内实现的单级积分清洗的滤波器结构,这种结构解决了传统积分梳妆滤波器中可能出现的积分器溢出问题,同时还可进行非整数倍的抽取变换.给出了一种无乘法半带滤波器的IIR实现结构,并对该滤波器性能进行了仿真,结果表明在输出过采样率大于4时基本不会影响系统误码性能.-Software for all-digital receiver decimation filter design, presents a suitable FPGA integ
Y1345977[1].PDF
- 关于fpga实现IIR滤波器资料文件，这是硕士生的论文，对论文的设计有很大帮助-IIR filter implementation on fpga data file, which is master' s thesis, the design of the thesis of great help
VHDL
- 基于FPGA的IIR滤波器的各模块VHDL程序- such as in science and project technique. Compared with FIR digital filter, IIR digital filter can get high selectivity with low factorial.
IIR-digital-filter-design-FPGA
- 基于FPGA的IIR低通数字滤波器设计 IIR low-pass digital filter design based on FPGA-IIR low-pass digital filter design based on FPGA
IIR
- 环路滤波器的FPGA实现，使用VERILOG语言，ISE13.2编译环境-The loop filter FPGA realizing, use VERILOG language, ISE13.2 compile environment
IIR_VerilogHDL
- 实现IIR红外解码的VHDL,通过遥控器遥控来发射红外线，FPGA接收到后进行解码并显示在数码管上面-a verilogHDL example to control IIR
FPGA-multiplier-on-chip
- 典型实例11.5 FPGA片上硬件乘法器的使用 软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 本实例实现一个IIR滤波器，并在ISE里面进行仿真。 \rtl目录里面是源文件 \project目录里面是工程-Typical examples 11.5 FPGA chip hardware multiplier using the software development environment: ISE 7.1i hardware d
lunwen
- 一个完整的基于FPGA的IIR低通滤波器的设计方案，是一个研究生论文-master and doctor dissertation
iir
- 基于FPGA的IIR滤波器实现，运行周期短，占用资源多，-IIR filter FPGA-based implementation, operation cycle is short, take more resources,
graduate
- 基于fpga的IIR和FIR滤波器实现，里面有DA和AD模块，已经下载到板子上验证。-IIR and FIR filter fpga-based implementation, which has DA and AD modules have been downloaded to authenticate to the board.
EDA
- 采用一种基于FPGA的IIR数字滤波器的设计方案,通过QuartusⅡ的设计平台，采用自顶向下的模块化设计思想将整个IIR数字滤波器分为：时序控制、延时、补码乘加和累加四个功能模块。分别对各模块采用VHDL进行描述后，进行了仿真和综合。-IIR digital filter using a FPGA-based design, analyzes the theory and design method of IIR digital filter, then through QuartusⅡ de
FPGA4JIIR
- 常用的数字滤波器有FIR数字滤波器和IIR数字滤波器｡ FIR数字滤波器具有精确的线性相位特性,在信号处理方面应用极为广泛,而且可以采用事先设计调试好的FIR数字滤波器IPCore来完成设计,例如Altera公司提供的针对Altera系列可编程器件的MegaCore,但是需要向Altera公司购买或申请试用版｡ 另外,对于相同的设计指标,FIR滤波器所要求的阶数比IIR滤波器高5~10倍,成本较高,而且信号的延迟也较大｡ IIR滤波器所要求的阶数不仅比FIR滤
Digital-signal-process-of-PFGA
- 数字信号处理 包括滤波器IIR FIR CORDIC的FPGA实现 资料中是VHDL语言 相应的配套包verilog程序-Digital signal processing includes a filter IIR FIR CORDIC on FPGA is VHDL language data corresponding supporting package verilog program
IIR_TEST
- fpga开发IIR滤波器，滤除声音中的噪声。-fpga development IIR filter, filter out the sound of the noise.
DIGITAL-SIGNAL-PROCESSING-WITH-FPGA
- 数字信号处理的FPGA实现最新版的源代码，涉及FFT变换、IIR、FIR数字滤波器等的verilog及vhdl代码-<digital signal processing with FPGA> (the latest version) . the source code involving FFT transform, IIR, FIR digital filters by verilog and vhdl.
IIRDirect
- 采用一种基于FPGA的IIR数字滤波器的设计方案：AD转换模块、IIR滤波模块、DA转换模块。(A design scheme of IIR digital filter based on FPGA is adopted: AD conversion module, IIR filter module and DA conversion module.)