搜索资源列表
DE2_i2sound
- DE2_i2sound.rar，大家快来下啊，做好了的IP核-DE2_i2sound.rar, everyone is breaking under ah, do a good job of the IP Core
DE2_Top
- DE2_Top.rar，做好了的IP核，大家开来下啊！-DE2_Top.rar, do a good job of the IP core, open to everyone under ah!
DE2_NET
- DE2_Top.rar，做好了的IP核，大家开来下啊！-DE2_Top.rar, do a good job of the IP core, open to everyone under ah!
DES_IP
- 是VDKL语言实现的DES算法，是一个IP核， 对于相关方面有很好的帮助-VDKL language of the DES algorithm is an IP core, related well with the help of
FPGA_common
- 关于FPGA的一些常识及含IP核的VHDL设计源代码。-on FPGA with some common sense and VHDL IP core design of the source code.
adma
- Wishbone dma ip core
DesignofTrainCommunicationAdapterBasedonSOPC
- 介绍了MVB总线帧结构，并完成了用于网络连接的MVB总线访问IP核的设计。-introduced the MVB bus frame structure, and completed the network connection for the MVB bus visit IP core design.
FFT_IP
- Xilinx FPGA 的IP核，实现FFT功能的-Xilinx FPGA IP core, FFT function
altera_lcd_controller
- quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
miniuart_vhdl
- 用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware descr iption language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.
mc8051_vhdl
- mcs51的vhdl IP核,是每个学习FPGA的必经之路，希望一起探讨-mcs51 the vhdl IP core, each is a must to learn FPGA, hoping to explore together
8051inVHDL
- 8051的VHDL IP核，很不错的东西-8051 VHDL IP core, a very good thing
ptc
- PWM/TIMER/COUNTER VHDL IP core-PWM / TIMER / COUNTER VHDL IP core
81i_radix2_xfft1024_v3_2
- xilinx FFT using ip core project navigator-xilinx ip using FFT core project navigator
minirisc
- minirisc Mini-RISC CPU-Microcontroller that is compatible with the PIC 16C57 from Microchip Mini-RISC CPU-Microcontroller ＩＰ核 -minirisc Mini-bit RISC CPU-Microcontroller that is compatible with the PIC 16C57 from Micro chip Mini-bit RISC CPU-Micr
simple_spi
- 一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchron
ip-core-verification-based-on-vhdl
- 在万方数据库中载的，有参考价值，自然科学基金支持项目-in popular database contains the reference value, the Natural Science Fund to support projects
LCD_IP_code
- LCD的通用驱动电路IP核设计..... -generic LCD driver circuit IP Core Design ...
my_ip_core
- 在quartusII下用verilog语言自己写的IP核，对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
led_pwm
- 用硬件描述语言实现的灯控IP核，可实现至少256种颜色的真彩变换。-using Hardware Descr iption Language lights control IP core can achieve at least 256 colors transform the sleekly.