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wishbone
- Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(
fundamentals-of-digital-logic-with-verilog-design
- fundamentals of digital logic with verilog design
logic-level-design
- 介绍了逻辑电平设计的知识和逻辑电平匹配的原则和应用-Describes the principles and application logic level design knowledge and logic level match
Verilog-design-experience
- 可编程逻辑基本设计原则,包括组合逻辑电路,时序逻辑电路-Programmable logic basic design principles, including the combinational logic circuits, sequential logic circuit
arbiter2
- The logic design of an efficient and fast round robin arbiter in Verilog or any other HDL language relies on the capability to find the next requestor to grant without losing cycles and with minimal logical stages. Using the fastest logic constructs
LD_Lect_1
- Lectures in Logic Design and Computer Architectures
LD_Lect_5
- Lectures in Logic Design and Computer Architectures
Verilog
- 夏宇闻数字逻辑设计，非常好的VHDL学习资料，不多说了-Xia Wen digital logic design, VHDL very good learning materials, not much to say
ARM-system-on-chip-Architecture
- The design of a general-purpose processor, in common with most engineering endeavours, requires the careful consideration of many trade-offs and compromises. In this chapter we will look at the basic principles of processor instruction set and
Development-of-Fuzzy-Logic-Power-System-Stabilize
- Design of Genetic Algorithm Based Fuzzy
light
- • 应用逻辑设计 1. 灯类 a. 主要属性和行为: 亮熄状态，关联图片资源对象，接受客户的亮熄要求 b. 类CLight 成员变量: m_state 成员函数: init, getState, setState 2. 开关类 a. 主要属性和行为: 关联所控的电灯CLight，接受客户的按动操作 b. 类CSwitch 成员变量: m_pLight 成员函数: init, push 3. 实例对象： 两个开关，一个灯；
DLD-projects
- Digital logic Design project stopwatch and clock esay to understand
Memoire2
- Design of an information retri system based on fuzzy logic-Design of an information retri system based on fuzzy logic
trafficlight
- 本课程设计侧重于逻辑电路设计同时采用VHDL硬件描述语言辅助完成对十字路口交通灯的功能仿真。在设计过程中，重点探讨了交通灯控制系统的设计思路和功能模块的划分，对设计过程中出现的问题详细进行。系统主要由四个模块组成：时钟分频模块、交通灯的控制及计时模块、扫描显示译码模块。-This course is designed to focus on the logic design using VHDL hardware descr iption language at the same time as
FPGA
- FPGA数字逻辑的设计，对于FPGA设计初学者有很大帮助-FPGA digital logic design, FPGA design for beginners is a great help
hpi
- 用CPLD实现4个C6201通过HPI接口互连的逻辑设计，包含VHDL程序-4 of C6201s through the HPI interface logic design of interconnection with CPLD, including the VHDL program
DB
- 健身房会员管理数据库的设计，其中包括逻辑设计、数据流等设计。-Gym membership management design, including logic design, data stream, such as design.
Interval-Type-2-Fuzzy-Logic-Toolbox
- This paper presents the development and design of a graphical user interface and a command line programming toolbox for construction, edition and observation of Interval Type-2 Fuzzy Inference Systems. The Interval Type-2 Fuzzy Logic System Toolbox (
calculation-logic-expressions
- c++ 的 数据结构 计算逻辑表达式真值 程序设计报告文档-C++ data structure calculation logic expressions of true value and general test report document design programming
ex5_mux
- 乘法器是众多数字系统中的基本模块。 从原理上说它属于组合逻辑范畴；但从工程实际设计上来说，它往往会利用时序逻辑设计的方法来实现，属于时序逻辑的范畴。通过这个实验使大家能够掌握利用 FPGA/CPLD 设计乘法器的思想，并且能够将我们设计的乘法器应用到实际工程中。 -The multiplier is the number of a digital system in the basic module. From the principle that it belongs to the combi