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design
- fuzzy logic controller design
top_PR
- 用户将使用具有局部重配置能力的ISE 12.1，进行综合HDL模块并完成设计。之后，使用PlanAhead12.1来布局规划设计，并内部调用执行和分析工具，包括：调用FPGA Editor查看设计实现 调用Constraint Editor创建时序约束；用Timing Analyzer进行时序分析。最后，用户可以用XUPV5开发板来进行硬件验证，并用iMPACT软件来下载全局和局部比特流。-Top-level design dynamically reconfigurable, static l
digital-IC
- 本文献全面介绍了数字逻辑设计的知识与技巧，欢迎下载！-This comprehensive introduction to the literature of digital logic design knowledge and skills are welcome to download!
6c8ec37a-3fd5-41e1-b3cf-a88af5f7c888
- 《华为静态时序分析与逻辑设计》《华为静态时序分析与逻辑设计》-Huawei static timing analysis and logic designHuawei static timing analysis and logic design
Fundamentals-of-Digital-Logic...mputer-Design-5th
- fundamental of Digital Logic and computer design ebooks for engineering-fundamental of Digital Logic and computer design ebooks for engineering
CEN-215-lab-project
- some projects on logic design
lect-4
- these slides for digital logic design
GP-IB-Code
- 本讲座分八讲：GP-IB标准接口逻辑设计、自动测试系统的组建、标准接口使用要领、接口功能配置和功能子集、GP-IB自动测试系统开发实例、GP-IB系统软件简介。是设计开发GP-IB系统的必备资料-The eight lectures about: GP-IB interface to standard logic design, automatic test system set up, the standard interface essentials, configuration and f
SMIC180MMRF
- 为了提供客户使用中芯国际0.18微米混合信号布局设计规则。这是混合信号和射频设计使用。逻辑设计，请参考2001年TD- LO18- DR。-To provide SMIC 0.18μm Mixed Signal layout design rules for customers’ use. This is for Mixed-Signal and RF design use. For Logic design, please refer to TD-LO18-DR-2001.
Final-Project-Report
- DIGITAL LOGIC DESIGN Project 7SEGMENT Desplyusing trainer Board
tanchishe
- 数字电路与逻辑设计综合实验，贪吃蛇游戏机的实验报告。本实验是用通过VHDL的代码编写，然后下载到EPM7128数字逻辑实验开发板上，用点阵显示老鼠，蛇，以及墙，用数码管显示倒计时以及得分的情况。最终实现老鼠的随机出现，蛇的移动以及吃老鼠得分，撞墙或触边即死。-Digital circuit and logic design experiment, experimental report of the Snake game consoles
Hua-Wei-ASICaVerilogaHardware
- 华为内部资料，整理分享给大家，内容如下： 1.Proverilog编码规范(草案) 2.华为_Verilog HDL电路设计指导书 3.华为内部培训资料linux 基础 4.华为同步电路设计规范 5.华为-硬件工程师 6.静态时序分析与逻辑设计- Huawei internal books, organize to share to you, reads as follows: 1.Proverilog coding standard (draft) 2.th
digital-logic-solutions-manual
- the solutions digital design 4th edition mano and cedelli
logic
- Verilog HDL逻辑与计算机设计基础实验全部试验报告，包括寄存器，定时器，全加器，同步时序电路，译码器等的实验。-Verilog HDL logic and computer design basic experiment all test reports, including registers, timers, full adder, synchronous sequential circuits, decoders and other experiments.
20090611105235857
- omron编程语言，中文输入格式，最新版的逻辑设计思路-The Omron programming language, Chinese input format, the latest version of the logic design
dengkong
- 数字电路与逻辑设计 用Quartus7.2 编辑的点阵灯控工程文件，让8*8的LED点阵能够按照不同的方式显示图像，数字等-Digital circuit and logic design using Quartus7.2 to design a cartoon by VHDL language.
Logic-fund.-with-MOSFETs
- this document serves a good intoduction to VLSI circuit design. it is a comprehensive descr iption of general circuit design using MOSFET. very useful for beginners in VLSI and mosfet circuit designers. -this document serves as a good intoduction to
book
- 本书是为“数字逻辑设计入门”课程编写的教科书，这门课是电子和计算机工程专业的基础课程-This book is written for digital logic design Getting Started "courses textbooks, this course is the foundation courses in electronics and computer engineering
Programming.Logic.and.Design
- 编程逻辑和设计，Farrell,.6ed,.Course,.201-Programming Logic and Design Comprehensive,Farrell,.6ed,.Course,.2011
shixu
- hspice进行时序逻辑设计 附带要求 源代码（经仿真）以及完成的实验报告-hspice timing logic design comes to source code (via simulation) and the completion of the experimental report