搜索资源列表
sram_test_OK
- 主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动，SRAM型号为IS61LV25616，程序语言为Verilog,开发环境为quartusII 7.0,为一工程，可直接下载到FPGA中，含电路图-Mainly based on FPGA (EP2C8Q208I8) driving under the SRAM, SRAM model IS61LV25616, programming language for Verilog, a development environment for
rom
- ROM模式的实现机制，基于verilog语言。-Implementation mechanism of ROM model, based on Verilog language.
4077mt48lc32m16a2
- 美光公司提供的DDR2的verilog仿真模型和do文件-Micron DDR2 provides the verilog simulation model and do file
mt48lc32m16a2
- SDRAM的仿真模型Verilog。用于美光mt48lc32m16a2，可在ModelSim下用。-Simulation Model of SDRAM
ddr3_model
- 一个verilog语言开发编写的简单的ddr3模型-A simple model ddr3, written with verilog language
gsm_ddc
- 基于GSM的数字下变频代码，能够直接生成Verilog代码，需要Synplify DSP 支持。-GSM DDC code. This Model can directly generate RTL code via Synplify DSP.
BPSK_receiver
- BPSK接收机设计，能够通过Synplify DSP直接生成Verilog代码。-BPSK Reciver model. This simulink model can generate RTL code via Synplify DSP.
dct2d
- 2D-DCT, 二维离散余弦变换模型。能够通过Synplify DSP生成Verilog代码 -2D-DCT model. This simulink model can generate RTL code via Synplify DSP.
bayer_sensor_mod
- 基于verilog编写的 CMOS sensor 模型，可以输出bayer 数据，尺寸可调-Verilog prepared by the CMOS sensor model, you can output bayer data, size adjustable
camera_model
- 原创的cmos sensor摄像头的verilog模型，可作为camera控制接口的仿真和验证。-Original verilog model cmos sensor camera can be used as simulation and verification camera control interface.
cp_model
- 原创协处理模型，异步并行接口，verilog实现，可作为仿真testbench用 -Co-processing model, asynchronous parallel interface, verilog achieve, can be used as a simulation testbench
wireless_FPGAcode
- 无线通信模块设计FPGA代码 包括matlab模型文件及verilog源代码-The wireless communication module design including FPGA code matlab verilog model file and source code
sd_spi_model.tar
- SD card, SPI mode, Verilog simulation model
FSM
- 用verilog语言编写的FSM文件，有限个状态及在这些状态之间的转移和动作等行为的数学模型，在计算机领域有着广泛的应用。-Mathematical model with verilog language FSM file transfer and finite number of states and actions between these states and other behavior in the computer industry has a wide range of appl
VER_I2C_EEPROM.ZIP
- EEPROM 的verilog仿真模型（cat24cxx系列）-verilog simulition Model of EEPROM,include cat24cxx
edge-detection1
- 基于FPGA开发环境，根据Sobel model算法，关于边缘检测的verilog代码。-the code of edge detection based on verilog.
uvm_axi-master
- axi uvm vip, verification model -axi system verilog
uart
- 该源码包是uart串口协议的verilog语言模型，主要包括了3个部分：波特率产生模块，uart接收模块，uart发送模块。(The source package is UART serial protocol Verilog language model, including 3 main parts: baud rate generation module, UART receiver module, UART transmission module.)
asyn_fifo
- 该源码包是异步fifo的Verilog语言模型，主要包括2个部分：异步fifo控制模块、测试文件。(The source package is asynchronous FIFO Verilog language model, including 2 main parts: asynchronous FIFO control module, test files.)
syn_fifo
- 该源码包是同步fifo的Verilog语言模型，主要包括2个部分：同步fifo控制模块、测试文件。(The source package is a synchronous FIFO Verilog language model, including 2 main parts: synchronous FIFO control module, test files.)