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AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
EEPROM_RD_WR.rar
- 本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v) ，这样可以有一个完整的EEPROM的控制模块和测试文件，本文件通过测试。,This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (e
modelsim_6.3f_6.4b_6.5_crck.ra
- 目前这个生成的key在modelsim se 6.3f 6.4b 6.5测试没问题。因为这几个版本是我逐步升级的，应该说从6.3f~6.5的都可以用。测试环境为windows xp sp3. vista没有测试。按理说是一样的。使用过程中遇到的一些问题的解决办法关于key里面生成中文字符的情况产生原因是，windows当前用户名和主机名是中文，修改之后重新生成一次。在安装的时候要设置环境变量LM_LICENSE_FILE，指向lincense的的路径和文件名。需要在cmd下使用modelsim的
flash02
- 一个我自己写的FPGA读写FLASH代码，在QUARTUS 下用verilog编写，falsh的型号是k9f5608u0d,经测试可以用。-I wrote a FLASH FPGA to read and write code, written in QUARTUS next with verilog, falsh model is k9f5608u0d, can be tested.
sdram 仿真模型
- sdram 仿真模型,用于verilog代码sdram行为级仿真-sdram modelsim model
IS63LV1024L
- ISSI SRAM IS63LV1024L 时序仿真模型-Verilog model of IS63LV1024L
counter60
- Verilog语言编写的模60计数器和testbench-Verilog language model 60 counters and testbench
verilog_intr
- Verilog Overview n Basic Structure of a Verilog Model n Components of a Verilog Module – Ports – Data Types – Assigning Values and Numbers – Operators – Behavioral Modeling • Continuous Assignments • Procedural Blocks –
counter16
- 一个verilog源代码，作用是计数器的建模。-A verilog source code, the role of the counter model.
serial1
- 串口简化verilog模型，固定波特率4.8k, 输入、输出使能输出-Verilog model of serial simplified
fir
- 利用Verilog语言编写的FPGA作为数字fir滤波器的程序，在编译器中调试通过，可以作为模块调用。-the model of fir digital cr which is written of verilog language.
parallel-fifo
- 利用Verilog语言编写的并行数据传输程序，在编译环境中编译通过。- the model of parallel data transmit which is written of verilog.
traffic_lights
- 一个关于交通灯的Verilog模型，可实现交通灯的功能仿真-A Verilog model of traffic lights, traffic lights to achieve the functional simulation
mt48lc4m32b2.v
- SDRAM VHDL/Verilog simulation model
state_mm
- 有限状态机源码，verilog语言编写。非常详细的示范了FSM状态机的编写。-Finite state machine source code, verilog language. A very detailed model of the FSM state machine preparation.
chap3
- 一些简单模型的verilog代码，对学习很有帮助-Some simple model of verilog code, very helpful for learning
chap5
- 一些简单模型的verilog代码，对学习很有帮助-Some simple model of verilog code, very helpful for learning
mux
- the multiplexer program are designed 2:1 and 4:1 in verilog model
uart
- the uart model is used to design the synthies and beherival model in verilog fpga
IS64LV6416L
- Asynchronous SRAM IS64LV6416L modelsim仿真模型-Asynchronous SRAM IS64LV6416L Verilog model