搜索资源列表
Mult
- 数据结构课上作业实现了一个多项式乘法的功能有注解-Job class data structure implements a polynomial function of multiplication comments
mult-object
- 国际重要期刊上最新的关于多目标优化问题的论文-Important international journals, the latest multi-objective optimization problems on paper
Mult
- 雷达多目标模拟器DRFM单元设计Multi-unit radar target simulator design DRFM-Multi-unit radar target simulator design DRFM
mult-Ping
- 多线程PING目的主机，并把结果集中显示-PING destination host multi-threaded, and the result set
functionPointers.tar
- Some simple use of function pointers in C. It declares 4 functions add, mult, sub, div and an array containting some pointers to these functions and in the main it demands to execute a function via the array.
mult
- 自己编写的乘法器 二进制4*4 vhdl环境 仿真通过-On time-multiplier binary imagecut.rar 4* 4 VHDL environmental simulation through
mult-acess
- tdma\fdma\cdma techique
89c2051-mult-mcu--communication
- 石油系统测井地面仪多机通讯、曼彻斯特软件解码、光电码盘软件计深组合程序-Oil well logging system of multi-machine communication device ground, Manchester decoding software, the software meter deep optical encoder combined program
mult
- 4比特乘法器的vhdl实现，含modelsim测试文件-4-bit multiplier vhdl implementation, including the test file modelsim
Mult-24x24
- Multiple 24x24bit=48bit 8051 microcontroller
mult
- 4级流水乘法器，本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计，编写VHDL程序完成了乘法器的功能设计，并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, write VHDL program to complete
mult
- 用verilog HDL语言实现的16位乘法器，以及tesrbench（测试文件）。-Verilog HDL language with 16-bit multiplier, and tesrbench (test file).
CreateThread
- Good Example for how to create Mult threading with Using Windows c-Good Example for how to create Mult -threading with Using Windows c++
Development-of-a-Mult
- Development of a Multi-Finger Hand for Humanoid Robot using Simulink Mechatronics Tool Chain
android-multimedia
- Android从入门到精通. 多媒体部分原代码以及文档。-android mult-media programming
Part3
- Quartus for 8x8 multiplier using lpm mult module from the library of parameterized modules in the Quartus II system.
A-Full-Duplex-Multi-channel-MAC-Protocol-for-Mult
- A Full Duplex Multi-channel MAC Protocol for Multi-hop Cognitive Radio Networks
multi_cycle_Verilog
- this code has written in verilog and it is about multi cycle mips processor .This code can do alot of jobs for examole,add ,addi ,addiu,and ,andi,ori ,mfhi.mfho,xor,slt,slti,ssw,lw,lui ,jal ,mult ,multu,... and it can multiply two input inter less th
MULT
- the document used to describe the verilog codes design floating point multiplier in coms design
small_rtos
- 源码是基于51单片机平台的微型操作系统，可以实现多任务调度。-the source is a micro operating system based on the 51 MCU platform,witch can finish the mult-task schedule.